S9S08SG8E2MTJ Datasheet, PDF (49/320 Pages) Freescale Semiconductor, Inc – MC9S08SG8 MC9S08SG4 Data Sheet Addendum

Chapter 4 Memory
High-page registers, shown in Table 4-3, are accessed much less often than other I/O and control registers
so they have been located outside the direct addressable memory space, starting at 0x1800.
Table 4-3. High-Page Register Summary (Sheet 1 of 2)
Address Register Name
0x1800 SRS
0x1801 SBDFR
0x1802 SOPT1
0x1803 SOPT2
0x1804 –
0x1805
Reserved
0x1806 SDIDH
0x1807 SDIDL
0x1808 Reserved
0x1809 SPMSC1
0x180A SPMSC2
0x180B–
0x180F
Reserved
0x1810 DBGCAH
0x1811 DBGCAL
0x1812 DBGCBH
0x1813 DBGCBL
0x1814 DBGFH
0x1815 DBGFL
0x1816 DBGC
0x1817 DBGT
0x1818 DBGS
0x1819–
0x181F
Reserved
0x1820 FCDIV
0x1821 FOPT
0x1822 Reserved
0x1823 FCNFG
0x1824 FPROT
0x1825 FSTAT
0x1826 FCMD
0x1827–
0x183F
Reserved
0x1840 PTAPE
0x1841 PTASE
0x1842 PTADS
0x1843 Reserved
0x1844 PTASC
Bit 7
6
POR
PIN
0
0
COPT
COPCLKS COPW
—
—
—
—
1
—
ID7
ID6
—
—
LVWF LVWACK
0
0
—
—
—
—
Bit 15
14
Bit 7
6
Bit 15
14
Bit 7
6
Bit 15
14
Bit 7
6
DBGEN ARM
TRGSEL BEGIN
AF
BF
—
—
—
—
DIVLD PRDIV8
KEYEN FNORED
—
—
0
0
FCBEF FCCF
—
—
—
—
0
0
0
0
0
0
—
—
0
0
5
4
3
2
COP
ILOP
ILAD
0
0
0
0
0
STOPE
0
0
IICPS
0
ACIC
0
0
—
—
—
—
—
—
—
—
—
—
ID11
ID10
ID5
ID4
ID3
ID2
—
—
—
—
LVWIE LVDRE LVDSE LVDE
LVDV
LVWV
PPDF PPDACK
—
—
—
—
—
—
—
—
13
12
11
10
5
4
3
2
13
12
11
10
5
4
3
2
13
12
11
10
5
4
3
2
TAG
BRKEN RWA RWAEN
0
0
TRG3
TRG2
ARMF
0
CNT3
CNT2
—
—
—
—
—
—
—
—
DIV
0
0
0
0
—
—
—
—
KEYACC
0
0
0
FPS
FPVIOL FACCERR
0
FBLANK
FCMD
—
—
—
—
—
—
—
—
—
—
PTAPE3 PTAPE2
—
—
PTASE3 PTASE2
—
—
PTADS3 PTADS2
—
—
—
—
0
0
PTAIF PTAACK
1
Bit 0
LVD
0
0
BDFR
0
0
T1CH1PS T1CH0PS
—
—
—
—
ID9
ID8
ID1
ID0
—
—
0
BGBE
—
PPDC
—
—
—
—
9
Bit 8
1
Bit 0
9
Bit 8
1
Bit 0
9
Bit 8
1
Bit 0
RWB RWBEN
TRG1
TRG0
CNT1
CNT0
—
—
—
—
SEC
—
—
0
0
FPDIS
0
0
—
—
PTAPE1
PTASE1
PTADS1
—
PTAIE
—
—
PTAPE0
PTASE0
PTADS0
—
PTAMOD
MC9S08SG8 MCU Series Data Sheet, Rev. 7
Freescale Semiconductor
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