S9S08SG8E2MTJ Datasheet, PDF (241/320 Pages) Freescale Semiconductor, Inc – MC9S08SG8 MC9S08SG4 Data Sheet Addendum

Chapter 16 Timer Pulse-Width Modulator (S08TPMV3)
Table 16-2. TPMV2 and TPMV3 Porting Considerations
Action
TPMV3
TPMV2
Write to TPMxCnTH:L registers¹
Any write to TPMxCNTH or TPMxCNTL registers
Read of TPMxCNTH:L registers¹
Clears the TPM counter
(TPMxCNTH:L) and the
prescaler counter.
Clears the TPM counter
(TPMxCNTH:L) only.
In BDM mode, any read of TPMxCNTH:L registers
Returns the value of the TPM If only one byte of the
counter that is frozen.
TPMxCNTH:L registers was
read before the BDM mode
became active, returns the
latched value of TPMxCNTH:L
from the read buffer (instead of
the frozen TPM counter value).
In BDM mode, a write to TPMxSC, TPMxCNTH or TPMxCNTL Clears this read coherency
mechanism.
Read of TPMxCnVH:L registers²
Does not clear this read
coherency mechanism.
In BDM mode, any read of TPMxCnVH:L registers
Returns the value of the
TPMxCnVH:L register.
If only one byte of the
TPMxCnVH:L registers was
read before the BDM mode
became active, returns the
latched value of TPMxCNTH:L
from the read buffer (instead of
the value in the TPMxCnVH:L
registers).
In BDM mode, a write to TPMxCnSC
Clears this read coherency Does not clear this read
mechanism.
coherency mechanism.
Write to TPMxCnVH:L registers
In Input Capture mode, writes to TPMxCnVH:L registers³
Not allowed.
Allowed.
In Output Compare mode, when (CLKSB:CLKSA not = 0:0),
writes to TPMxCnVH:L registers³
Update the TPMxCnVH:L
registers with the value of
their write buffer at the next
change of the TPM counter
(end of the prescaler
counting) after the second
byte is written.
Always update these registers
when their second byte is
written.
In Edge-Aligned PWM mode when (CLKSB:CLKSA not = 00),
writes to TPMxCnVH:L registers
Update the TPMxCnVH:L
registers with the value of
their write buffer after both
bytes were written and when
the TPM counter changes
from (TPMxMODH:L - 1) to
(TPMxMODH:L).
Note: If the TPM counter is a
free-running counter, then
this update is made when the
TPM counter changes from
0xFFFE to 0xFFFF.
Update after both bytes are
written and when the TPM
counter changes from
TPMxMODH:L to 0x0000.
MC9S08SG8 MCU Series Data Sheet, Rev. 7
Freescale Semiconductor
237