S9S08SG8E2MTJ Datasheet, PDF (312/320 Pages) Freescale Semiconductor, Inc – MC9S08SG8 MC9S08SG4 Data Sheet Addendum

Appendix A Electrical Characteristics
A.12.3 SPI
Table A-15 and Figure A-14 through Figure A-17 describe the timing requirements for the SPI system.
Table A-15. SPI Electrical Characteristic
Num¹ C
Rating²
Symbol
Min
Temp Rated³
Max
Unit
Standard
AEC Grade
0
Cycle time
1
D
Master t_SCK
2
2048
t_cyc
x
x
Slave t_SCK
4
—
t_cyc
Enable lead time
2
D
Master t_Lead
—
1/2
t_SCK
x
x
Slave _tLead
1/2
—
t_SCK
Enable lag time
3
D
Master t_Lag
—
1/2
t_SCK
x
x
Slave _tLag
1/2
—
t_SCK
4
D
Clock (SPSCK) high time
Master and Slave
t_SCKH
1/2 t_SCK – 25
—
ns
x
x
5
D
Clock (SPSCK) low time
Master and Slave
t_SCKL
1/2 t_SCK – 25
—
ns
x
x
Data setup time (inputs)
6
D
Master t_SI(M)
30
—
ns
x
x
Slave _tSI(S)
30
—
ns
Data hold time (inputs)
7
D
Master t_HI(M)
30
—
ns
x
x
Slave _tHI(S)
30
—
ns
8
D Access time, slave⁴
t_A
0
40
ns
x
x
9
D Disable time, slave⁵
t_dis
—
40
ns
x
x
Data setup time (outputs)
10
D
Master t_SO
25
—
ns
x
x
Slave _tSO
25
—
ns
Data hold time (outputs)
11
D
Master t_HO
–10
—
ns
x
x
Slave _tHO
–10
—
ns
Operating frequency
12
D
Master f_op
Slave
f_op
f_Bus/2048
dc
5⁶
f_Bus/4
MHz
x
x
1 _{Refer to Figure A-14 through Figure A-17.}
2 _{All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. All timing assumes slew}
rate control disabled and high drive strength enabled for SPI output pins.
3 _{Electrical characteristics only apply to the temperature rated devices marked with x.}
4 _{Time to data active from high-impedance state.}
5 _{Hold time to high-impedance state.}
6 _{Maximum baud rate must be limited to 5 MHz due to input filter characteristics.}
MC9S08SG8 MCU Series Data Sheet, Rev. 7
308
Freescale Semiconductor