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S9S08SG8E2MTJ Datasheet, PDF (303/320 Pages) Freescale Semiconductor, Inc – MC9S08SG8 MC9S08SG4 Data Sheet Addendum
Appendix A Electrical Characteristics
A.9 Internal Clock Source (ICS) Characteristics
Table A-9. ICS Frequency Specifications (Temperature Range = –40 to 125C Ambient)
Nu
m
C
Rating
Temp Rated1
Symbol
Min
Typ
Max
Unit
Standard
AEC
Grade 0
Internal reference frequency - factory
1 P trimmed
at VDD = 5 V
fint_ft
— 31.25 — kHz
x
x
Internal reference frequency -
2 P untrimmed2
fint_ut
25
36 41.66 kHz
x
x
3
P
Internal reference frequency - user
trimmed
fint_t
31.25 — 39.0625 kHz
x
x
4 D Internal reference startup time
tirefst
—
55
100 s
x
x
DCO output frequency range -
5
—
untrimmed1 
value provided for reference: fdco_ut =
fdco_ut
25.6 36.86 42.66 MHz
x
x
1024  fint_ut
6
D
DCO output frequency range -
trimmed
32
—
40 MHz
x
fdco_t
32
—
36 MHz
x
Resolution of trimmed DCO output
7 D frequency at fixed voltage and
fdco_res_t
—
0.1 0.2 %fdco
x
x
temperature (using FTRIM)
Resolution of trimmed DCO output
8 D frequency at fixed voltage and
fdco_res_t
—
0.2 0.4 %fdco
x
x
temperature (not using FTRIM)
Total deviation from actual trimmed
9 P DCO output frequency over voltage
and temperature
fdco_t
—
+ 0.5
– 1.0
1.5 %fdco
x
—
+ 0.5
– 1.0
3 %fdco
x
Total deviation of trimmed DCO output
10 D frequency over fixed voltage and
fdco_t
—
0.5 1 %fdco
x
x
temperature range of 0C to 70 C
11 D FLL acquisition time 3
tacquire
1
ms
x
x
DCO output clock long term jitter (over
12 D 2mS interval) 4
CJitter
—
0.02
0.2 %fdco
x
x
1 Electrical characteristics only apply to the temperature rated devices marked with x.
2 TRIM register at default value (0x80) and FTRIM control bit at default value (0x0).
3 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or
changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used
as the reference, this specification assumes it is already running.
4 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal.
Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter
percentage for a given interval.
MC9S08SG8 MCU Series Data Sheet, Rev. 7
Freescale Semiconductor
299