S9S08SG8E2MTJ Datasheet, PDF (242/320 Pages) Freescale Semiconductor, Inc – MC9S08SG8 MC9S08SG4 Data Sheet Addendum

Chapter 16 Timer Pulse-Width Modulator (S08TPMV3)
Table 16-2. TPMV2 and TPMV3 Porting Considerations (continued)
Action
TPMV3
TPMV2
In Center-Aligned PWM mode when (CLKSB:CLKSA not =
00), writes to TPMxCnVH:L registers⁴
Update the TPMxCnVH:L Update after both bytes are
registers with the value of written and when the TPM
their write buffer after both counter changes from
bytes are written and when TPMxMODH:L to
the TPM counter changes (TPMxMODH:L - 1).
from (TPMxMODH:L - 1) to
(TPMxMODH:L).
Note: If the TPM counter is a
free-running counter, then
this update is made when the
TPM counter changes from
0xFFFE to 0xFFFF.
Center-Aligned PWM
When TPMxCnVH:L = TPMxMODH:L⁵
When TPMxCnVH:L = (TPMxMODH:L - 1)⁶
TPMxCnVH:L is changed from 0x0000 to a non-zero value⁷
TPMxCnVH:L is changed from a non-zero value to 0x0000⁸
Produces 100% duty cycle. Produces 0% duty cycle.
Produces a near 100% duty Produces 0% duty cycle.
cycle.
Waits for the start of a new
PWM period to begin using
the new duty cycle setting.
Changes the channel output at
the middle of the current PWM
period (when the count
reaches 0x0000).
Finishes the current PWM
period using the old duty
cycle setting.
Finishes the current PWM
period using the new duty
cycle setting.
Write to TPMxMODH:L registers in BDM mode
In BDM mode, a write to TPMxSC register
Clears the write coherency
mechanism of
TPMxMODH:L registers.
Does not clear the write
coherency mechanism.
1 _{For more information, refer to Section 16.3.2, “TPM-Counter Registers (TPMxCNTH:TPMxCNTL) .” [SE110-TPM case 7]}
2 _{For more information, refer to Section 16.3.5, “TPM Channel Value Registers (TPMxCnVH:TPMxCnVL).”}
3 _{For more information, refer to Section 16.4.2.1, “Input Capture Mode .”}
4 _{For more information, refer to Section 16.4.2.4, “Center-Aligned PWM Mode.”}
5 _{For more information, refer to Section 16.4.2.4, “Center-Aligned PWM Mode.” [SE110-TPM case 1]}
6 _{For more information, refer to Section 16.4.2.4, “Center-Aligned PWM Mode.” [SE110-TPM case 2]}
7 _{For more information, refer to Section 16.4.2.4, “Center-Aligned PWM Mode.” [SE110-TPM case 3 and 5]}
8 _{For more information, refer to Section 16.4.2.4, “Center-Aligned PWM Mode.” [SE110-TPM case 4]}
16.1.4 Migrating from TPMV1
In addition to Section 16.1.3, “TPMV3 Differences from Previous Versions,” keep in mind the following
considerations when migrating from a device that uses TPMV1.
• You can write to the Channel Value register (TPMxCnV) when the timer is not in input capture
mode for TPMV2, not TPMV3.
MC9S08SG8 MCU Series Data Sheet, Rev. 7
238
Freescale Semiconductor