33910 Datasheet, PDF (39/44 Pages) Freescale Semiconductor, Inc – LIN System Basis Chip with 2x60mA High Side Drivers

FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
Interrupt Mask Register - IMR
This register allow to mask some of interrupt sources. The
respective flags within the ISR will continue to work but will
not generate interrupts to the MCU. The 5V Regulator over-
temperature prewarning interrupt and under-voltage (VSUV)
interrupts can not be masked and will always cause an
interrupt.
Writing to the interrupt mask register (IMR) will return the
ISR.
Table 26. Interrupt Mask Register - $E
C3
C2
C1
C0
Write
HSM
-.
LINM
VMM
Reset
Value
1
1
1
1
Reset
Condition
POR
HSM - High Side Interrupt Mask
This write-only bit enables/disables interrupts generated in
the high side block.
1 = HS Interrupts Enabled
0 = HS Interrupts Disabled
LINM - LIN Interrupts Mask
This write-only bit enables/disables interrupts generated in
the LIN block.
1 = LIN Interrupts Enabled
0 = LIN Interrupts Disabled
VMM - Voltage Monitor Interrupt Mask
This write-only bit enables/disables interrupts generated in
the voltage monitor block. The only maskable interrupt in the
voltage monitor block is the V_SUP over-voltage interrupt.
1 = Interrupts Enabled
0 = Interrupts Disabled
Interrupt Source Register - ISR
This register allows the MCU to determine the source of
the last interrupt or wake-up respectively. A read of the
register acknowledges the interrupt and leads IRQ pin to
high, in case there are no other pending interrupts. If there
are pending interrupts, IRQ will be driven high for 10µs and
then be driven low again.
This register is also returned when writing to the interrupt
mask register (IMR).
Table 27. Interrupt Source Register - $E/$F
S3
S2
S1
S0
Read
ISR3
ISR2
ISR1
ISR0
ISRx - Interrupt Source Register
These read-only bits indicate the interrupt source following
Table 28. If no interrupt is pending than all bits are 0.
In case more than one interrupt is pending, than the
interrupt sources are handled sequentially multiplex.
Table 28. Interrupt Sources
Interrupt Source
ISR3 ISR2 ISR1 ISR0
none maskable
maskable
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
no interrupt
-
-
Voltage monitor interrupt
(Low-voltage and VDD over-temperature)
-
no interrupt
L1 wake-up from Stop Mode-
HS interrupt (Over-temperature)
Reserved
LIN interrupt (RXSHORT, TXDOM, LIN OT, LIN
OC) or LIN wake-up
Voltage monitor interrupt
(High-voltage)
Forced wake-up
Priority
none
highest
lowest
Analog Integrated Circuit Device Data
Freescale Semiconductor
33910
39