33910 Datasheet, PDF (36/44 Pages) Freescale Semiconductor, Inc – LIN System Basis Chip with 2x60mA High Side Drivers

FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
High Side Control Register - HSCR
This register controls the operation of the high side drivers.
Writing to this register returns the High Side Status Register
(HSSR).
Table 17. High Side Control Register - $6
C3
C2
C1
C0
Write PWMHS2 PWMHS1
HS2
HS1
Reset
Value
0
0
0
0
Reset
Condition
POR
POR, Reset Mode, ext_reset, HSx
over-temp or (VSOV & HVSE)
PWMHSx - PWM Input Control Enable
This write-only bit enables/disables the PWMIN input pin
to control the high side switch. The high side switch must be
enabled (HSx bit).
1 = PWMIN input controls HS1 output.
0 = HSx is controlled only by SPI.
HSx - High Side Switch Control.
This write-only bit enables/disables the high side switch.
1 = HSx switch on.
0 = HSx switch off.
High Side Status Register - HSSR
This register returns the status of the high side switch and
is also returned when writing to the HSCR.
Table 18. High Side Status Register - $6/$7
S3
S2
S1
S0
Read HS2OP HS2CL HS1OP HS1CL
High Side thermal shutdown
A thermal shutdown of the high side drivers is indicated by
setting the HSxOP and HSxCL bits simultaneously.
HSxOP - High Side Switch Open-Load Detection
This read-only bit signals that the high side switch is
conducting current below a certain threshold indicating
possible load disconnection.
1 = HSx Open Load detected (or thermal shutdown)
0 = Normal
HSxCL - High Side Current Limitation
This read-only bit indicates that the high side switch is
operating in current Limitation Mode.
1 = HSx in current limitation (or thermal shutdown)
0 = Normal
Timing Control Register - TIMCR
This register is a double purpose register which allows to
configure the watchdog and the cyclic sense periods. Writing
to the TIMCR will also return the WDSR.
Table 19. Timing Control Register - $A
C3
C2
C1
C0
Write
CS/WD
WD2
CYST2
WD1
CYST1
WD0
CYST0
Reset
Value
-
0
0
0
Reset
Condition
-
POR
CS/WD - Cyclic Sense or Watchdog Prescaler Select.
This write-only bit selects which prescaler is being written
to, the cyclic sense prescaler or the watchdog prescaler.
1 = Cyclic Sense Prescaler selected
0 = Watchdog Prescaler select
WDx - Watchdog Prescaler
This write-only bits selects the divider for the watchdog
prescaler and therefore selects the watchdog period in
accordance with Table 20. This configuration is valid only if
windowing watchdog is active.
Table 20. Watchdog Prescaler
WD2 WD1 WD0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Prescaler Divider
1
2
4
6
8
10
12
14
33910
36
Analog Integrated Circuit Device Data
Freescale Semiconductor