33910 Datasheet, PDF (14/44 Pages) Freescale Semiconductor, Inc – LIN System Basis Chip with 2x60mA High Side Drivers

ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 5.5V ≤ V_SUP ≤ 18V, -40°C ≤ T_A ≤ 125°C for the 33910 and -40°C ≤ T_A ≤ 85°C for the
34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at T_A = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
L1 INPUT
Wake-up Filter Time
STATE MACHINE TIMING
t _WUF
8.0
20
38
µs
Delay Between CS LOW-to-HIGH Transition (at End of SPI Stop Command)
and Stop Mode Activation⁽⁴⁰⁾
t _STOP
–
µs
–
5.0
Normal Request Mode Timeout (see Figure 12, page 19)
Delay Between SPI Command and HS Turn On⁽⁴¹⁾
9V < V_SUP < 27V
t _{NR TOUT}
110
150
205
ms
t _S-ON
–
µs
–
10
Delay Between SPI Command and HS Turn Off⁽⁴¹⁾
9V < V_SUP < 27V
t _S-OFF
–
µs
–
10
Delay Between Normal Request and Normal Mode After a Watchdog Trigger
Command (Normal Request Mode)⁽⁴⁰⁾
t _SNR2N
–
µs
–
10
Delay Between CS Wake-up (CS LOW to HIGH) in Stop Mode and:
Normal Request Mode, VDD ON and RST HIGH
First Accepted SPI Command
µs
t _WUCS
9.0
15
80
t _WUSPI
90
—
N/A
Minimum Time Between Rising and Falling Edge on the CS
t _2CS
4.0
—
—
µs
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR NORMAL SLEW RATE - 20.0KBIT/SEC^{(42), (43)}
Duty Cycle 1: D1 = t_{BUS_REC(MIN)}/(2 x t_BIT), t_BIT = 50µs
7.0V ≤ V_SUP ≤ 18V
D1
0.396
—
—
Duty Cycle 2: D2 = t_{BUS_REC(MAX)}/(2 x t_BIT), t_BIT = 50µs
7.6V ≤ V_SUP ≤ 18V
D2
—
—
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR SLOW SLEW RATE - 10.4KBIT/SEC^(42),(44)
0.581
Duty Cycle 3: D3 = t_{BUS_REC(MIN)}/(2 x t_BIT), t_BIT = 96µs
7.0V ≤ V_SUP ≤ 18V
D3
µs
0.417
—
—
Duty Cycle 4: D4 = t_{BUS_REC(MAX)}/(2 x t_BIT), t_BIT = 96µs
7.6V ≤ V_SUP ≤ 18V
D4
µs
—
—
0.590
Notes
40. This parameter is guaranteed by process monitoring but, not production tested.
41. Delay between turn on or off command (rising edge on CS) and HS ON or OFF, excluding rise or fall time due to external load.
42. Bus load R_BUS and C_BUS 1.0nF / 1.0kΩ, 6.8nF / 660Ω, 10nF / 500Ω. Measurement thresholds: 50% of TXD signal to LIN signal threshold
defined at each parameter. See Figure 6, page 17.
43. See Figure 7, page 17.
44. See Figure 8, page 17.
33910
14
Analog Integrated Circuit Device Data
Freescale Semiconductor