33910 Datasheet, PDF (37/44 Pages) Freescale Semiconductor, Inc – LIN System Basis Chip with 2x60mA High Side Drivers

FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
CYSTx - Cyclic Sense Period Prescaler Select
This write-only bits selects the interval for the wake-up
cyclic sensing together with the bit CYSX8 in the
configuration register (CFR) (see page 38).
This option is only active if the high side switch is enabled
when entering in Stop or Sleep Mode. Otherwise a timed
wake-up is performed after the period shown in Table 21.
Table 21. Cyclic Sense Interval
CYSX8⁽⁵⁶⁾ CYST2 CYST1 CYST0
Interval
X
0
0
0
No Cyclic Sense
0
0
0
1
20ms
0
0
1
0
40ms
0
0
1
1
60ms
0
1
0
0
80ms
0
1
0
1
100ms
0
1
1
0
120ms
0
1
1
1
140ms
1
0
0
1
160ms
1
0
1
0
320ms
1
0
1
1
480ms
1
1
0
0
640ms
1
1
0
1
800ms
1
1
1
0
960ms
1
1
1
1
1120ms
Notes
56. bit CYSX8 is located in configuration register (CFR)
Watchdog Status Register
This register returns the watchdog status information and
is also returned when writing to the TIMCR.
Table 22. Watchdog Status Register - $A/$B
S3
S2
S1
S0
Read WDTO WDERR WDOFF WDWO
WDTO - Watchdog Time Out
This read-only bit signals the last reset was caused by
either a watchdog timeout or by an attempt to clear the
watchdog within the window closed.
Any access to this register or the TIMCR will clear the
WDTO bit.
1 = Last reset caused by watchdog timeout
0 = None
WDERR - Watchdog Error
This read-only bit signals the detection of a missing
watchdog resistor. In this condition the watchdog is using the
internal, lower precision timebase. The windowing function is
disabled.
1 = WDCONF pin resistor missing
0 = WDCONF pin resistor not floating
WDOFF - Watchdog Off
This read-only bit signals that the watchdog pin connected
to GND and therefore disabled. In this case watchdog
timeouts are disabled and the device automatically enters
Normal Mode out of Reset. This might be necessary for
software debugging and for programming the Flash memory.
1 = Watchdog is disabled
0 = Watchdog is enabled
WDWO - Watchdog Window Open
This read-only bit signals when the watchdog window is
open for clears. The purpose of this bit is for testing. Should
be ignored in case WDERR is High.
1 = Watchdog window open
0 = Watchdog window closed
Analog Multiplexer Control Register - MUXCR
This register controls the analog multiplexer and selects
the divider ration for the L1 input divider.
Table 23. Analog Multiplexer Control Register -$C
C3
C2
C1
C0
Write
L1DS
MX2
MX1
MX0
Reset
Value
1
0
0
0
Reset
Condition
POR
POR, Reset Mode or ext_reset
L1DS - L1 Analog Input Divider Select
This write-only bit selects the resistor divider for the L1
analog input. Voltage is internally clamped to VDD.
0 = L1 Analog divider: 1
1 = L1 Analog divider: 3.6 (typ.)
Analog Integrated Circuit Device Data
Freescale Semiconductor
33910
37