33899 Datasheet, PDF (12/26 Pages) Freescale Semiconductor, Inc – Programmable H-Bridge Power IC

FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33899 is a programmable H-Bridge, power integrated
circuit (IC) designed to drive DC motors or bi-directional
solenoid controlled actuators, such as throttle control or
exhaust gas recirculation actuators. It is particularly well
suited for the harsh environment found in automotive power
train systems.
The key characteristic of this versatile driver is
configurability. The selectable slew rate permits the customer
to choose the slew rate needed for performance and noise
suppression. The Serial Peripheral Interface (SPI) allows the
system microprocessor to clear the fault register, select a
programmable current limit and select the slew rate. A unique
fault restart feature allows the part to be configured to
maintain limited functionality even in the presence of some
faults.
The 33899 is designed to drive a bi-directional DC motor
using pulse-width modulation (PWM) for speed and torque
control. A current mirror output provides an analog feedback
signal proportional to the load current. SPI diagnostic
reporting includes open circuit, short-to-battery, short-to-
ground, die temperature range and under-voltage.
FUNCTIONAL PIN DESCRIPTION
VIGNP INPUT (VIGNP)
VIGNP is the primary power input for the H-Bridge. The
input voltage is 0V to 26.5V (40V during a load dump
transient). This pin must be externally protected against
application of a reverse voltage (through an external inverted
N-channel MOSFET, diode, or switched relay).
+ 5.0V INPUT (VCC)
+5.0V power input is required to power the internal analog
circuitry and the +3.3V internal regulator.
+ 3.3V INPUT (VCCL)
A +3.3V internal regulator powers the internal digital
circuitry. The internal supply cannot be used as a power
source by any other IC in the system. This output can be
overdriven by an external supply. The internal supply
requires a 0.47μF capacitor on this output to insure proper
startup sequencing when coming out of sleep mode.
LOGIC BIAS INPUT (VDDQ)
VDDQ supplies the level shifted bias voltage for the logic
level outputs designed to be read by the microprocessor. This
pin will apply the logic supply voltage to DO and LSCMP
making the output logic levels compliant to logic systems
from 3V to over 5V.
OUTPUTS (S1 AND S0)
The S1 and S0 outputs drive the bi-directional DC motor.
Each output has two internal N-channel MOSFETs
connected in a half-bridge configuration between VIGNP and
ground. Only one internal MOSFET is on at any one time for
each output. The FWD, REV, and PWM inputs control the
state of the H-Bridge. The turn on / off slew times are
determined by the selected RS resistor value and the SPI
slew time register contents (refer to Table 8, page 22).
OUTPUT POLARITY CONTROL (FWD/REV INPUTS)
The FWD and REV inputs determine the direction of
current flow in the H-Bridge by directing the PWM input to one
of the low side MOSFETs (refer to Table 5). When a change
in the current direction is commanded via the
microprocessor, the PWM must switch from one low side
MOSFET to the other without shoot-through current in the H-
Bridge. The gate voltage of the low side MOSFETs must drop
below and remain below the gate threshold voltage for the
“dead time” before either of the high side MOSFETs is
commanded on. At no time are the high side and low side
MOSFETs simultaneously on at the same side of the H-
Bridge. The FWD and REV inputs have 50μA pull-downs to
ground that disable all the outputs should an open circuit
condition occur.
FWD
0
0
1
1
Table 5. FWD / REV Truth Table
REV
Current Direction
0
Off
1
Reverse
0
Forward
1
Off
33899
12
Analog Integrated Circuit Device Data
Freescale Semiconductor