FIN324C Datasheet, PDF (9/23 Pages) Fairchild Semiconductor – 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Displays

Application Diagrams
Baseband
Processor
/CS
PCLK
R,G,B[5:0]
Hsync_D/C
Vsync
SD
OE
RESET
GPIO
/STBY
/RES
CKSEL
VDDP1 VDDS/A
C2
E2 F2
VDDP VDDS/A
A4 _STRB0
B4 _STRB1
D4:G6
C4
C3
A3
B3
A2
B2
A1
VDDP1
D3
F3
G3
G2
B1
DP[17:0]
CNTL[0]
CNTL[1]
CNTL[2]
CNTL[3]
CNTL[4]
CNTL[5]
R/W
M/S
PAR/SPI
/STBY
/RES
CKSEL
CKS+ ^D1
CKS- ^E1
DS+ ^G1
DS- ^F1
E3
D2
C1
VDDP2 VDDS/A
C2
E2 F2
VDDP VDDS/A
WCLK0 ^A4
WCLK1 ^B4
DP[17:0] ^D4:G6
CNTL[0] ^C4
CNTL[1] ^C3
G1
F1
CKS+ _CNTL[2] ^A3
CKS- _CNTL[3] B3
D1
E1
DS+
DS-
CNTL[4] ^A2
CNTL[5] ^B2 NC
R/W ^A1 NC
M/S ^D3
PAR/SPI ^F3
E3
SLEW ^G3
D2
/RES ^G2
C1
H ^B1
Sub-Display
Data [7:0]
D/C
/CS
RESET
P/S
R/W
Main Display
PCLK
R,G,B [5:0]
Hsync
Vsync
SD
OE
VDDP2
Edge Rate Control Option
SLEW must be connected
to VDDS or GND for low
power.
Notes:
1. Write-only Interface.
2. Assumes BGA die on display.
3. /CS used to strobe sub-display data.
4. PCLK used for RGB mode.
5. Pin numbers for BGA package.
Figure 6. Dual Display with Parallel RGB Main Display and 6800-Style Microcontroller Sub-Display
Baseband
Processor
/WE
PCLK
R,G,B[5:0]
Hsync_ADDR
Vsync
SD
OE
RESET
/CS
GPIO
/STBY
/RES
CKSEL
VDDP1 VDDS/A
C2
E2 F2
VDDP VDDS/A
A4 _STRB0
B4 _STRB1
D4:G6
C4
C3
A3
B3
A2
B2
A1
VDDP1
D3
F3
G3
G2
B1
DP[17:0]
CNTL[0]
CNTL[1]
CNTL[2]
CNTL[3]
CKS+ ^D1
CKS- ^E1
CNTL[4]
CNTL[5]
R/W
M/S
DS+ ^G1
DS- ^F1
PAR/SPI
/STBY
E3
/RES
D2
CKSEL
C1
VDDP2 VDDS/A
C2
E2 F2
VDDP VDDS/A
WCLK0 ^A4
WCLK1 ^B4
DP[17:0] ^D4:G6
CNTL[0] ^C4
CNTL[1] ^C3
G1
F1
CKS+ _CNTL[2] ^A3
CKS- _CNTL[3] B3
D1 _DS+
E1 _DS-
CNTL[4] ^A2
CNTL[5] ^B2
R/W ^A1 NC
M/S ^D3
PAR/SPI ^F3
E3
SLEW ^G3
D2
/RES ^G2
C1
H ^B1
Sub-Display
Data [7:0]
ADDR
/WE
RESET
P/S
/CS
Main Display
PCLK
R,G,B [5:0]
Hsync
Vsync
SD
OE
VDDP2
Edge Rate Control Option
SLEW must be connected
to VDDS or GND for low
power.
Notes:
1.
2.
3.
4.
5.
Write-only Interface.
Assumes BGA die on display.
/WE used to strobe sub-display data.
PCLK used for RGB mode.
Pin numbers for BGA package.
Figure 7. Dual Display with Parallel RGB Main Display and x86-Style Microcontroller Sub-Display
© 2006 Fairchild Semiconductor Corporation
FIN324C Rev. 1.0.5
9
www.fairchildsemi.com