FIN324C Datasheet, PDF (14/23 Pages) Fairchild Semiconductor – 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Displays

Power Characteristics
Symbol Parameter
I_{DYN_SER}
Dynamic
Current of
Master Device
I_{DYN_DES}
I_{BRST_M}
I_{BRST_S}
I_STBY
Dynamic
Current of
Slave Device
Burst Standby
Current of
Master
Burst Standby
Current of
Slave
Standby
Current
Test Conditions
V_DDA/S=2.75V, M/S=1,
V_DDP=1.8V, /STBY=1,
/RES=1
V_DDA/S=2.75V, M/S=0
V_DDP=1.8V, /STBY=1,
/RES=1, C_L= 0pF
5.44MHz
12.00MHz
15.00MHz
5.44MHz
12.00MHz
15.00MHz
V_DDA/S=2.75V, V_DDP=1.8V, M/S=1,
/STBY=1, /RST=1, No STROBE Signal,
C_L=0pF
V_DDA/S=2.75V, V_DDP=1.8V, M/S=0,
/STBY=1, /RST=1, No STROBE Signal,
C_L=0pF
Serializer or Deserializer
V_DDS/A=V_DDP=3.0V, /STBY=0, /RST=1,
STRB1=5.44MHz, C_L=0pF
Min.
Typ.
4
7
8
5
8
10
1.1
1.8
Max. Units
mA
mA
mA
mA
10
µA
AC Operating Characteristics
Values are provided for over-supply voltage and operating temperature ranges, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min. Typ. Max. Units
f_WSTRB0
Write Strobe Frequency CKSEL=0 STRB0 (PRS1)
0
8
f_WSTRB1
Write Strobe Frequency CKSEL=1 STRB1
0
15
f_RSTRB
t_R, t_F
Read Strobe Frequency
Input Edge Rates⁽⁶⁾
0
2
40
t_S1
Write Mode Setup Time DP before STRBn ↑, See Figure 11
5
t_H1
Write Mode Hold Time
DP after STRBn ↑, See Figure 11
15
t_S2
READ Mode Setup Time
R/W, CNTL before STRBn ↓
See Figure 12
0
t_H2
t_S-STRB
READ Mode Hold Time
R/W, CNTL after STRBn ↓
See Figure 12
16
CKSEL to STRBn Setup
Time
CKSEL before active edge STRBn⁽⁷⁾
See Figure 13, Figure 14
50
t_{SKEW_DS-CKS}
Allowed DS-CKS Input
Signal Skew
Deserializer Mode
Max. Internal Oscillator Frequency
See Figure 18
-150 0
150
Notes:
6. Characterized, but not production tested.
7. Active edge of strobe is the rising edge for a write transaction and the falling edge for a read transaction.
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ps
© 2006 Fairchild Semiconductor Corporation
FIN324C Rev. 1.0.5
14
www.fairchildsemi.com