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FIN324C Datasheet, PDF (7/23 Pages) Fairchild Semiconductor – 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Displays
LV-CMOS I/O Signals
System Control Signals
The system control signals consist of M/S, /RES,
/STBY(SLEW), PAR/SPI, and CKSEL. For connectivity
flexibility, these signals are over-voltage tolerant to the
maximum supply voltage connected to the device. This
allows these signals to be tied HIGH to either a VDDS or
VDDP supply without static current consumption. These
signals are all LV-CMOS inputs and should never be
allowed to float.
Parallel I/O Signals
The parallel data port signals consist of the DP[17:0],
CNTL[5:0], R/W, and STRB1(0)(WCLK1(0)) signals.
These signals have built-in voltage translation, allowing
the signals of the master and slave to be connected to
different VDDP supply voltages.
Serial I/O Signals
CTL I/O Technology
The serial I/O is implemented using Fairchild’s
proprietary differential CTL I/O technology. During data
transfers, the serial I/O are powered up to a normal
operating mode around .5V. Upon completion of a data
transfer, the serial I/O goes to a lower power mode
around VDDS.
Serial I/O Orientation Logic
The serial I/O signal traces should not cross between
the master and the slave. The pin locations have been
designed to eliminate the need to cross traces. See
Table 7, Figure 4 and Figure 5.
Table 7. Serial Pin Orientation
Master (M/S=1) (Pad/Pin #)
Package
CKS+
CKS-
DS-
DS+
MLP
2
3
6
7
BGA
D1
E1
F1
G1
Slave (M/S=0) (Pad/Pin #)
CKS+
CKS-
DS-
DS+
7
6
3
2
G1
F1
E1
D1
6
G
5 43 2 1
DS+
F
DS-
E
CKS-
D
CKS+
C
BGA
B
Master
A
A
B
C
<DS+>
D
<DS->
<CKS->
E
BGA
Slave F
<CKS+>
G
1 2 34 5 6
21
22 MLP
23 Master
24
25
26
27
28
29
30
M/S 10
PAR/SPI 9
/RES 8
DS+ 7
DS- 6
VDDA 5
VDDS 4
CKS- 3
CKS+ 2
CKSE L(H)
1
1 CKSEL(H)
2 (DS+)
3 (DS-)
4 VDD S
5 VDD A
6 (CKS-)
7 (CKS+)
8 /RES
9 PAR/SPI
10 M/S
Figure 4. BGA Pair
Figure 5. MLP Pair
30
MLP 29
Slave 28
27
26
25
24
23
22
21
© 2006 Fairchild Semiconductor Corporation
FIN324C Rev. 1.0.5
7
www.fairchildsemi.com