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| FIN324C Datasheet, PDF (17/23 Pages) Fairchild Semiconductor – 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Displays | |||
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AC Reset and Standby Timing
Symbol
Parameter
Test Conditions
Min. Typ. Max. Units
tVDD-OFF
Power Down Relative
to /RES(18)
See Figure 20
20
µs
tSTRB-RES
/RES after last
STRBn â
M/S=0 or 1, /STBY=1, R/W=0(19)
See Figure 20
0
ns
tSTRB-STBY
Standby time after last M/S=0 or 1, /STBY=1(20)
strobe
See Figure 20
200
ns
tRES-OFF
Master/Slave Reset
Disable Time
M/S=1 /STBY=1, /RES=â
See Figure 20
15
20
µs
Allowed Skew
tVDD-SKEW
between VDDP and
Figure 19
-â
VDDA/S(21)
tVDD-RES
Minimum Reset Low
Time After VDD Stable
M/S=0 /STBY=1, /RES=â(22)
See Figure 19
20
tRES-STBY
/STBY Wait Time
After /RES â
M/S=1 /RES=1, /STBY=â
See Figure 19
20
tDVALID
/STBY to Active Edge
of Strobe
M/S=0 /RES=1(23)
See Figure 19
30
+â
ms
µs
µs
µs
Notes:
18. Timing allows the device to completely reset prior to powering down.
19. Internal reset on the filter allows assertion prior to completion of read or write date transfer.
20. Timing ensures that last write transaction is complete prior to going into standby.
21. VDDA/S must power up together. VDDP may power-up relative to VDDA/S in any order without static power being
consumed. Guaranteed by characterization.
22. /RES signal should be held low for minimum time specified after supplies go HIGH. It is recommended that /RES
be held low during the power supply ramp.
23. STRBn must be held off until internal oscillator has stabilized.
© 2006 Fairchild Semiconductor Corporation
FIN324C Rev. 1.0.5
17
www.fairchildsemi.com
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