FIN324C Datasheet, PDF (10/23 Pages) Fairchild Semiconductor – 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Displays

Application Diagrams (Continued)
Baseband
Processor
/CS
PCLK
R,G,B[5:0]
Hsync
Vsync
SD
D/C
SDAT
SCLK
GPIO
/STBY
/RES
CKSEL
VDDP1 VDDS/A
C2
E2 F2
VDDP VDDS/A
A4 _STRB0
B4 _STRB1
D4:G6
C4
C3
A3
B3
A2
B2
A1
VDDP1
D3
F3
G3
G2
B1
DP[17:0]
CNTL[0]
CNTL[1]
CNTL[2]
CNTL[3]
CKS+ ^D1
CKS- ^E1
CNTL[4]
CNTL[5]
R/W
M/S
DS+ ^G1
DS- ^F1
PAR/SPI
/STBY
E3
/RES
D2
CKSEL
C1
Module 1
VDDP2 VDDS/A
C2
E2 F2
VDDP VDDS/A
WCLK0 ^A4
WCLK1 ^B4
DP[17:0] ^D4:G6
CNTL[0] ^C4
CNTL[1] ^C3
G1
F1
CKS+ _CNTL[2] ^A3
CKS- _CNTL[3] B3
D1
E1
DS+
DS-
CNTL[4] ^A2 NC
CNTL[5] ^B2 NC
R/W ^A1 NC
M/S ^D3
PAR/SPI ^F3
E3
SLEW ^G3
D2
/RES ^G2
C1
H ^B1
F6 SCLK DP[6]
E5 SDAT DP[7]
Sub-Display
SCLK
SDAT
/CS
D/C
RESET
P/S
Main Display
PCLK
R,G,B [5:0]
Hsync
Vsync
SD
VDDP2
Edge Rate Control Option
SLEW must be connected
to VDDS or GND for low
power.
Notes:
1.
2.
3.
4.
5.
6.
Write-only interface (R/W hardwaired LOW).
SPI sub-display interface PAR/SPI=LOW for bot.h master and slave.
SCLK connected to CNTL[5]; SDAT connected to CNTL[4].
Shared data pin SDAT; SCLK connections on sub-display.
Assumes BGA die on display.
Pin numbers for BGA package.
Figure 8. Dual Display with RGB Main Display and SPI Sub-Display Interface
Baseband
Processor
/CS0
/CS1
DATA[17:0]
D/C
RESET 0
RESET 1
R/W
GPIO
/STBY
/RES
CKSEL
VDDP1 VDDS/A
C2
E2 F2
VDDP VDDS/A
A4 _STRB0
B4 _STRB1
D4:G6
C4
C3
A3
B3
A2
B2
A1
VDDP1_D3
F3
G3
G2
B1
DP[17:0]
CNTL[0]
CNTL[1]
CNTL[2]
CNTL[3]
CNTL[4]
CNTL[5]
R/W
M/S
PAR/SPI
/STBY
/RES
CKSEL
CKS+ ^D1
CKS- ^E1
DS+ ^G1
DS- ^F1
E3
D2
C1
Module 1
VDDP2 VDDS/A
C2
E2 F2
VDDP VDDS/A
WCLK0 ^A4
WCLK1 ^B4
DP[17:0] ^D4:G6
CNTL[0] ^C4
CNTL[1] ^C3
G1
F1
CKS+ _CNTL[2] ^A3
CKS- _CNTL[3] B3 _NC
D1
E1
DS+
DS-
CNTL[4] ^A2 _NC
CNTL[5] ^B2 NC
R/W ^A1
M/S ^D3
PAR/SPI ^F3
E3
SLEW ^G3
D2
/RES ^G2
C1
H ^B1
Sub-Display
DATA [17:0]
D/C
/CS0
RESET 0
P/S
R/W
Main Display
/CS1
DATA[17:0]
D/C
RESET 1
R/W
VDDP2
Edge Rate Control Option
SLEW must be connected
to VDDS or GND for low
power.
Notes:
1.
2.
3.
4.
R/W interface. R/W signal connected to ba.seband microprocessor.
Assumes BGA die on display.
PAR/SPI connected HIGH to indicate parallel operation.
Pin numbers for BGA pack.age.
Figure 9. R/W Dual Display with Parallel Microcontroller Main Display and Sub-Display
© 2006 Fairchild Semiconductor Corporation
FIN324C Rev. 1.0.5
10
www.fairchildsemi.com