FIN324C Datasheet, PDF (6/23 Pages) Fairchild Semiconductor – 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Displays

System Control Pins
(M/S) Master / Slave Selection: A given device can be
configured as a master or slave device based on the
state of the M/S pin.
Table 1. Master/Slave
M/S
0
1
Configuration
Slave Mode
Master Mode
(PAR/SPI) SPI Mode Selection: The PAR/SPI signal
configures STRB0(WCLK0) for SPI mode write operation.
STRB1(WCLK1) always operates in parallel mode.
Control signals CNTL[5:0] all pass in SPI mode. In SPI
mode, the SCLK signal is used to strobe the serializer.
SPI mode supports SPI writes only.
Table 2. Channel 0 PAR/SPI Configuration
PAR
/SPI
M/S=1 MASTER
M/S=0 SLAVE
SDAT=CNTL[4] SDAT=DP[7] & CNTL[4]
0 SCLK=CNTL[5] SCLK=DP[6] & CNTL[5]
/CS=STRB0
/CS=WCLK0
1
Parallel Mode
Parallel Mode
(CKSEL) Strobe Selection Signal: The CKSEL signal
exists only on the master device and determines which
strobe signal is active. The active strobe signal is
selected by CKSEL and PAR/SPI inputs.
Table 3. PAR/SPI
PAR CKSEL
/SPI
0
0
0
1
1
0
1
1
Master
Strobe
Source
CNTL[5]
STRB1
STRB0
STRB1
Slave Strobe
Source
DP[6] & CNTL[5]
WCLK1
WCLK0
WCLK1
(/RES, /STBY) Reset and Standby Mode Functionality:
Reset and standby mode functionality is determined by
the state of the /RES and /STBY signals for the master
device and the /RES and internal standby-detect signal for
the slave device. The /RES control signal has a filter that
rejects spurious pulses on /RES.
Table 4. Reset and Standby Modes
/RES /STBY⁽³⁾
Master
Slave
0
X
Reset Mode Reset Mode
1
0
Standby Mode
Standby
Mode⁽³⁾
1
1
Operating Mode
Operating
Mode
Note:
3. The slave device is put into standby mode through
control signals sent from the master device.
Table 5. Reset and Standby Mode States
Pin
Master
Slave
Reset / Standby Reset
Slave
Standby
DP[17:0]
CNTL[5:0]
STRB[0:1]
(WCLK[0:1])
Disabled
Disabled
Disabled
Low
Low
High
Last data
Last data
High
(SLEW) Slew Control: The slew control operates only
when in slave mode. This signal changes the edge rate
of the DP[17:0], CNTL[5:0], R/W, WCLK1, and WCLK0
signals to optimize edge rate for the load being driven.
Master read mode outputs have “slow” edge rates.
Table 6. Slew Rate Control
/STBY (SLEW)
0
1
Slave M/S=0
“Slow”
“Fast”
© 2006 Fairchild Semiconductor Corporation
FIN324C Rev. 1.0.5
6
www.fairchildsemi.com