FIN324C Datasheet, PDF (3/23 Pages) Fairchild Semiconductor – 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Displays

Pin Definitions
Pin
I/O
#
Type Pins
Description of Signals
Chip-Level Control Signals
M/S
IN
1
LV-CMOS Master/Slave Control Input:
M/S=1 MASTER, M/S =0 SLAVE
/RES
LV_CMOS RESET signal and power-down signal
IN
1
/RES=0: Resets and powers down all circuitry
/RES=1: Device enabled
/STBY(SLEW)
IN
LV-CMOS standby signal or output slew rate signal:
M/S=1: /STBY
1
M/S=0: RSLEW
/STBY=0: Device powered down
RSLEW=1: Fast edge rate
RSLEW=0: Slow edge rate
PAR/SPI
LV-CMOS parallel / SPI display interface
IN
1
Tells the SerDes it is interfacing with a sub-display with a SPI interface
PAR/SPI=1: Parallel Interface
PAR/SPI=0: SPI Interface using STRB0(WCLK0)
CKSEL(H)
LV-CMOS Input: Master clock source select input.
When M/S=1: CKSEL (passed in serial stream)
IN
1
CKSEL=1: STRB1(WCLK1) Active
CKSEL=0: STRB0(WCLK0) Active
When M/S=0: This pin must be tied to VDDP.
Parallel Interface Signals Master Functionality (Slave Functionality)
DP[17:0]
LV-CMOS data I/O. I/O direction controlled by M/S pin and R/W
internal state.
DP[6]({SCLK})
DP[7]({SDAT})
I/O
18
DP[6] SPI mode SCLK signal pin when PAR/SPI=0 (Slave Only)
DP[7] SPI mode SDAT signal pin when PAR/SPI=0(Slave Only)
CNTL[5:0]
{SCLK}CNTL[5]
I/O
{SDAT}CNTL[4]
LV-CMOS data I/O. I/O direction controlled by M/S pin
M/S=1: Inputs
6
M/S=0: Outputs
In SPI mode, CNTL[5] is SCLK; CNTL[4] is SDAT for master and slave
LV-CMOS data I/O. I/O direction controlled by M/S pin.
M/S=1: Input
R/W
I/O
1
M/S=0: Output
Functional operation:
R/W=1: Read
R/W=0: Write
STRB0(WCLK0)
I/O
LV-CMOS data I/O. Function controlled by M/S pin.
1
M/S=1: STRB0 Input
M/S=0: WCLK0 Output
STRB1(WCLK1)
I/O
LV-CMOS Data I/O. Function controlled by M/S pin.
1
M/S=1: STRB1 Input
M/S=0: WCLK1 Output
© 2006 Fairchild Semiconductor Corporation
FIN324C Rev. 1.0.5
3
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