FIN324C Datasheet, PDF (8/23 Pages) Fairchild Semiconductor – 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Displays

Master/Slave READ/WRITE transactions
During a write data transfer, DP[17:0], CNTL[5:0],
R/W, and CKSEL are serialized and transmitted by
the master to the slave. The slave receives the
signals, outputs the data and control signals, and
generates either a WCLK0 or WCLK1 pulse based on
the value of CKSEL. The CKSEL signal must remain
stable throughout the transaction.
Read transactions have two phases: The Read-
Control Phase, where CNTL[5:0], R/W, CKSEL are
transmitted to the deserializer; and the Read-Data
Phase, where the DP[17:0] signals of the slave are
read and transmitted back to the master device. The
slave device generates its own strobe signal for
latching in the data. Slave data must be valid prior to
the WCLKn signal going HIGH.
Master Serializer Operation (Read Control Phase)
When the R/W signal is asserted HIGH and the
STROBE signal transitions LOW, the Read-Control
Phase of the read cycle is initiated. The R/W signal
must not transition until the READ cycle completes.
For a READ transaction, only eight control signals are
captured. The 18 DP bits are ignored during the
READ operation. The following sequence must occur
for data to be serialized properly:
Microcontroller Read Sequence (Read-Control Phase):
1. Selects input strobe source (CKSEL= 0 or 1).
2. CPU sends signals (R/W=1, CKSEL, CNTL[5:0]).
3. STROBE Signal transitions LOW.
4. Captures control bits.
5. Device leaves burst standby mode.
6. Serializes and sends control bits.
7. Serializer turns around serial I/O waiting for data.
Slave Deserializer Operation (Read-Control Phase)
Microcontroller Read Sequence (Read-Control Phase):
1. Deserializer leaves burst standby mode.
2. Begins receiving valid serial stream.
3. Captures data from serial transfer.
4. Turns around serial I/O.
5. Internally decodes that this is a READ transaction
and the WCLK to use.
6. Outputs control signals, 3-state DP data bus.
7. Outputs falling edge of WCLK pulse.
Slave Serializer Read Operation (Read-Data Phase)
The slave serializer is enabled on the tail end of the
Read-Control Phase of operation. The operation of
the serializer is identical to the master serialization
except that the strobe signal is generated internally
and only the data bits DP[17:0] are captured.
Microcontroller Read Sequence (Read-Data Phase):
1. Display device outputs data onto DP bus on
falling edge of WCLK.
2. Captures parallel data on generated rising edge
of WCLK signal.
3. Serializes data stream.
4. DP signals are sent.
5. CNTL signals are sent as 0.
6. Turns serial I/O around, awaiting next
transaction.
Master Deserializer Read Operation (Read-Data Phase):
Initially the deserializer is in low-power operation. The
deserializer wakes up when it detects CKSO+ and
CKSO- transition from LOW to normal operating range.
Microcontroller Read Sequence (Read-Data Phase):
1. Master deserializer wakes up when the CKSI+
and CKSI- signals reach valid levels.
2. Begins receiving valid serial stream.
3. Outputs data DP[17:0].
4. Turns serial I/O around and goes to burst standby
mode.
5. Processor asserts rising edge of strobe signal to
capture data.
SPI WRITE transaction
SPI mode is activated by asserting the PAR/SPI signal
low on both the master and slave device. A SPI write is
only performed when CKSEL=0. During a SPI
transaction, SCLK must be connected to CNTL[5] and is
the strobe source for serialization. SDAT is assumed to
be on CNTL[4] and all of the remaining control signals
and STRB0 are serialized. STRB0 should be connected
to the SPI mode chip select.
On the rising edge of SCLK, all eight control signals
(CNTL[5:0], R/W, CKSEL) are captured and serialized.
The data signals are not sent. The /CS signal on STRB0 is
captured in bit position CNTL[5]. The deserializer captures
the serial stream and outputs it to the parallel port.
As shown in Table 2, SDAT and SCLK are output on
multiple pins. The DP[7] and DP[6] connections can be
used for displays with dual-mode operation and the data
pins are multiplexed with the SPI signals. CNTL[5] and
CNTL[4] signals can be used when the signals are not
multiplexed.
© 2006 Fairchild Semiconductor Corporation
FIN324C Rev. 1.0.5
8
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