FIN324C Datasheet, PDF (15/23 Pages) Fairchild Semiconductor – 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Displays

AC Deserializer Specifications
Values are provided for over-supply voltage and operating temperature ranges, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min. Typ. Max. Units
t_R0, t_F0
t_R1, t_F1
t_CS
t_PDV-WR0
t_PDV-WR1
t_PDV-RD
t_PDV-SPI
t_PWL-WR0
t_PWL-WR1
t_PWL-RD
t_PWL-SPI
Output Edge Rates of
WCLK0,WCLK1
Output Edge Rates of R/W,
DP[17:0] CNTL[5:0]
CNTL[5:0],R/W to Falling
Edge of WCLKn
DP, CNTL to WCLK0 ↑
DP, CNTL to WCLK1 ↑
CNTL to WCLKn ↑
Data, CNTL to SCLK ↑
WCLK0 Pulse Width Low
Write Mode
WCLK1 Pulse Width Low
Write Mode
Pulse Width Low of WCLK
Read Mode
Pulse Width Low of WCLK
SPI Mode
SLEW=0, CL=5pF 20% to 80%⁽⁸⁾
SLEW=0; C_L=10pF 30% to 70%⁽⁸⁾
SLEW=1, C_L=5pF 20% to 80%⁽⁸⁾
SLEW=0, C_L=5pF 20% to 80%⁽⁸⁾
SLEW=0; C_L=10pF 30% to 70%⁽⁸⁾
SLEW=1, C_L=5pF 20% to 80%⁽⁸⁾
M/S=0⁽⁹⁾, See Figure 15
PAR/SPI=1⁽⁹⁾, See Figure 15
PAR/SPI=1⁽⁹⁾, See Figure 15
PAR/SPI=1⁽⁹⁾, See Figure 17
PAR/SPI=0⁽⁹⁾, See Figure 16
M/S=0, R/W=0, PAR/SPI=1^(9,10)
See Figure 15
M/S=0, R/W=0, PAR/SPI=1^(9,10)
See Figure 15
M/S=0, R/W=1, PAR/SPI=1^(9,10)
See Figure 17
M/S=0, R/W=0, PAR/SPI=0^{(9, 10)}
See Figure 16
8
17
12
ns
10
8
22
12
ns
17
0
4
ns
50 60
ns
18 24
ns
200 224
ns
40 60
ns
50 56
ns
18 20
ns
200 220
ns
40 56
ns
Notes:
8. Characterized, but not production tested.
9. Indirectly tested through serial clock frequency and serial data bit tests.
10. Pulse width low WCLKn measurements are measured at 30% of VDDP. Measurements apply when SLEW=0 or
SLEW=1.
© 2006 Fairchild Semiconductor Corporation
FIN324C Rev. 1.0.5
15
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