FIN24C_06 Datasheet, PDF (9/25 Pages) Fairchild Semiconductor – uSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer

Deserializer Operation Mode
The operation of the deserializer is only dependent upon the data received on the DSI data signal pair and the CKSI
clock signal pair. The following two sections describe the operation of the deserializer under two distinct serializer
source conditions. References to the CKREF and STROBE signals refer to the signals associated with the serializer
device used in generating the serial data and clock signals that are inputs to the deserializer.
When operating in this mode, the internal serializer circuitry is disabled, including the parallel data input buffers. If there
is a CKREF signal provided, the CKSO serial clock continues to transmit bit clocks. Upon device power-up (S1 or S2 =
1), all deserializer output data pins are driven LOW until valid data is passed through the deserializer.
Deserializer Operation: DIRI = 0
(Serializer Source:
CKREF = STROBE)
When the DIRI signal is asserted LOW, the device is configured as a deserializer.
Data is captured on the serial port and deserialized through use of the bit clock
sent with the data. The word boundary is defined in the actual clock and data sig-
nal. Parallel data is generated at the time the word boundary is detected. The fall-
ing edge of CKP occurs approximately six bit times after the next falling edge of
CKSI. The rising edge of CKP goes HIGH approximately 13 bit times after CKP
goes LOW. When no embedded word boundary occurs, no pulse is generated on
CKP and CKP remains HIGH.
WORD n-1
WORD n
WORD n+1
DSI b₂₄ b₂₅ b₂₆ b₁
CKSI
b₆ b₇ b₈ b₉
b₁₉ b₂₀
b₂₄ b₂₅ b₂₆ b₁ b₂
CKPO
DP[1:24] WORD n-2
WORD n-1
WORD n
Figure 7. Deserializer Timing Diagram (Serializer Source: CKREF equals STROBE)
Deserializer Operation: DIRI = 0
(Serializer Source:
CKREF does not = STROBE)
The logical operation of the deserializer remains the same if the CKREF is equal
in frequency to the STROBE or at a higher frequency than the STROBE. The
actual serial data stream presented to the deserializer, however, differs because it
has non-valid data bits sent between words. The duty cycle of CKP varies based
on the ratio of the frequency of the CKREF signal to the STROBE signal. The fre-
quency of the CKP signal is equal to the STROBE frequency. The falling edge of
CKP occurs six bit times after the data transition. The LOW time of the CKP signal
is equal to half (13 bit times) of the CKREF period. The CKP HIGH time is equal to
STROBE period – half of the CKREF period. Figure 8 is representative of a wave-
form that could be seen when CKREF is not equal to STROBE. If CKREF is signif-
icantly faster, additional non-valid data bits occur between data words.
WORD n-1
WORD n
WORD n+1
DSI b24 b25 b26 0
CKSI
CKPO
DP[1:24] WORD n-2
0
6 bit times
b_j b_j+1
b_j+13 b_j+14
13 bit times
WORD n-1
b₂₄ b₂₅ b₂₆ 0 0
WORD n
Figure 8. Deserializer Timing Diagram (Serializer Source: CKREF does not equal STROBE)
©2005 Fairchild Semiconductor Corporation
FIN24C Rev. 1.0.2
9
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