FIN24C_06 Datasheet, PDF (17/25 Pages) Fairchild Semiconductor – uSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer

Notes:
4. Typical Values are given for V_DD = 2.775V and T_A = 25°C. Positive current values refer to the current flowing into
device and negative values refer to current flowing out of pins. Voltage is referenced to GROUND unless otherwise
specified (except ΔV_OD and V_OD).
5. Skew is measured from either the rising or falling edge of CKSO clock to the rising or falling edge of data (DSO).
Signals are edge aligned. Both outputs should have identical load conditions for this test to be valid.
6. The power-down time is a function of the CKREF frequency prior to CKREF being stopped HIGH or LOW and the
state of the S1/S2 mode pins. The specific number of clock cycles required for the PLL to be disabled varies based
on the operating mode of the device.
7. Signals are transmitted from the serializer source synchronously. In some cases, data is transmitted when the clock
remains at a high state. Skew should only be measured when data and clock are transitioning at the same time. Total
measured input skew is a combination of output skew from the serializer, load variations, and ISI and jitter effects.
8. Rising edge of CKP appears approximately 13 bit times after the falling edge of the CKP output. Falling edge of CKP
occurs approximately eight bit times after a data transition or six bit times after the first falling edge of CSKO. Variation
of the data with respect to the CKP signal is due to internal propagation delay differences of the data and CKP path
and propagation delay differences on the various data pins. If the CKREF is not equal to STROBE for the serializer,
the CKP signal does not maintain a 50% duty cycle. The low time of the CKP remains 13 bit times.
Control Logic Timing Controls
Symbol
Parameter
Test Conditions
Min. Typ. Max. Units
t_{PHL_DIR},
t_{PLH_DIR}
t_PLZ, t_PHZ
Propagation Delay
DIRI-to-DIRO
Propagation Delay
DIRI-to-DP
DIRI LOW-to-HIGH or HIGH-to-LOW
DIRI LOW-to-HIGH
17.0 ns
25.0 ns
t_PZL, t_PZH Propagation Delay
DIRI-to-DP
DIRI HIGH-to-LOW
25.0 ns
t_PLZ, t_PHZ
t_PZL, t_PZH
Deserializer Disable Time:
S0 or S1 to DP
Deserializer Enable Time:
S0 or S1 to DP
DIRI = 0,
S1(2) = 0 and S2(1) = LOW-to-HIGH, Figure 30
DIRI = 0,⁽¹⁰⁾
S1(2) = 0 and S2(1) = LOW-to-HIGH, Figure 30
25.0 ns
2.0 µs
t_PLZ, t_PHZ Serializer Disable Time: DIRI = 1,
S0 or S1 to CKSO, DS S1(2) = 0 and S2(1) = HIGH-to-LOW, Figure 28
25.0 ns
t_PZL, t_PZH Serializer Enable Time:
S0 or S1 to CKSO, DS
DIRI = 1,
S1(2) and S2(1) = LOW-to-HIGH, Figure 28
65.0 ns
Note:
9. Deserializer enable time includes the amount of time required for internal voltage and current references to stabilize.
This time is significantly less than the PLL lock time and does not impact overall system startup time.
Capacitance
Symbol
C_IN
C_IO
C_IO-DIFF
Parameter
Capacitance of Input Only Signals,
CKREF, STROBE, S1, S2, DIRI
Capacitance of Parallel Port Pins
DP[1:12]
Capacitance of Differential I/O Signals
Test Conditions
DIRI = 1, S1 = S2 = 0,
V_DDP = 2.5V
DIRI = 1, S1 = S2 = 0,
V_DDP = 2.5V
DIRI = 0, S1 = S2 = 0,
V_DDP = 2.775V
Min. Typ. Max. Units
2.0
pF
2.0
pF
2.0
pF
©2005 Fairchild Semiconductor Corporation
FIN24C Rev. 1.0.2
17
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