FIN24C_06 Datasheet, PDF (10/25 Pages) Fairchild Semiconductor – uSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer

Embedded Word Clock Operation
The FIN24C sends and receives serial data source syn-
chronously with a bit clock. The bit clock has been modi-
fied to create a word boundary at the end of each data
word. The word boundary has been implemented by
skipping a LOW clock pulse. This appears in the serial
clock stream as three consecutive bit times where signal
CKSO remains HIGH.
To implement this sort of scheme, two extra data bits are
required. During the word boundary phase, the data tog-
gles either HIGH-then-LOW or LOW-then-HIGH depen-
dent upon the last bit of the actual data word. Table 2
provides some examples of the actual data word and the
data word with the word boundary bits added. Note that
a 24-bit word is extended to 26 bits during serial trans-
mission. Bit 25 and Bit 26 are defined with-respect-to Bit
24. Bit 25 is always the inverse of Bit 24 and Bit 26 is
always the same as Bit 24. This ensures that a “0” → “1”
and a “1” → “0” transition always occurs during the
embedded word phase where CKSO is HIGH.
The serializer generates the word boundary data bits
and the boundary clock condition and embeds them into
the serial data stream. The deserializer looks for the end
of the word boundary condition to capture and transfer
the data to the parallel port. The deserializer only uses
the embedded word boundary information to find and
capture the data. These boundary bits are stripped prior
to the word being sent out the parallel port.
LVCMOS Data I/O
The LVCMOS input buffers have a nominal threshold
value equal to half V_DDP. The input buffers are only oper-
ational when the device is operating as a serializer.
When the device is operating as a deserializer, the
inputs are gated off to conserve power.
The LVCMOS 3-STATE output buffers are rated for a
source/sink current of 2mAs at 1.8V. The outputs are
active when the DIRI signal is asserted LOW. When the
DIRI signal is asserted HIGH, the bi-directional LVCMOS
I/Os are in a HIGH-Z state. Under purely capacitive load
conditions, the output swings between GND and V_DDP.
Unused LVCMOS input buffers must be tied off to either
a valid logic LOW or a valid logic HIGH level to prevent
static current draw due to a floating input. Unused
LVCMOS outputs should be left floating. Unused
bidirectional pins should be connected to GND through a
high-value resistor. If a FIN24C devices is configured as
an unidirectional serializer, unused data I/O can be
treated as unused inputs. If the FIN24C is hardwired as a
deserializer, unused date I/O can be treated as unused
outputs.
From
Deserializer
DP[n]
To
Serializer
From
Control
Figure 9. LVCMOS I/O
Differential I/O Circuitry
The FIN24C employs FSC proprietary CTL I/O technol-
ogy. CTL is a low-power, low-EMI differential swing I/O
technology. The CTL output driver generates a constant
output source and sink current. The CTL input receiver
senses the current difference and direction from the out-
put buffer to which it is connected. This differs from
LVDS, which uses a constant current source output, but
a voltage sense receiver. Like LVDS, an input source
termination resistor is required to properly terminate the
transmission line. The FIN24C device incorporates an
internal termination resistor on the CKSI receiver and a
gated internal termination resistor on the DS input
receiver. The gated termination resistor ensures proper
termination regardless of direction of data flow. The rela-
tively greater sensitivity of the current sense receiver of
CTL allows it to work at much lower current drive and a
much lower voltage.
During power-down mode, the differential inputs are dis-
abled and powered down and the differential outputs are
placed in a HIGH-Z state. CTL inputs have an inherent
fail-safe capability that supports floating inputs. When
the CKSI input pair of the serializer is unused, it can reli-
ably be left floating. Alternately both of the inputs can be
connected to ground. CTL inputs should never be con-
nected to V_DD. When the CKSO output of the deserial-
izer is unused, it should be allowed to float.
Table 2. Word Boundary Data Bits
24-Bit Data Words
Hex
Binary
FFFFFFh 1111 1111 1111 1111 1111 1111b
555555h
0101 0101 0101 0101 01010 0101b
xxxxxxh
0xxx xxxx xxxx xxxx xxxx xxxxb
xxxxxxh
1xxx xxxx xxxx xxxx xxxx xxxxb
©2005 Fairchild Semiconductor Corporation
FIN24C Rev. 1.0.2
24-Bit Data Word with Word Boundary
Hex
Binary
2FFFFFFh 10 1111 1111 1111 1111 1111 1111b
1555555h 01 0101 0101 0101 0101 0101 0101b
1xxxxxxh 01 0xxx xxxx xxxx xxxx xxxx xxxxb
2xxxxxxh 10 1xxx xxxx xxxx xxxx xxxx xxxxb
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