FIN24C_06 Datasheet, PDF (18/25 Pages) Fairchild Semiconductor – uSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer

AC Loading and Waveforms
Input
DS+
RL/2
R_L/2
DS-
V_OD
VOS
DUT
+
–
DUT
+
–
100Ω Termination
+
–
VGO
Figure 14. Differential CTL Output DC Test Circuit
Figure 15. CTL Input Common Mode Test Circuit
T
DP[1:12]
666h
999h
666h
CKREF
CKS0-
CKS0+
DS+
DS- ^{b13 b14 b1 b2}
01
b₆ b₇ b₈
01 0
b₁₁ b₁₂ b₁ b₂
0110
b₆ b₇ b₈
10 1
b₁₁ b₁₂ b₁ b₂
10
Note:
The “worst-case” test pattern produces a maximum toggling of internal digital circuits, CTL I/O and LVCMOS I/O with the PLL operating at the reference
frequency, unless otherwise specified. Maximum power is measured at the maximum V_DD values. Minimum values are measured at the minimum V_DD values.
Typical values are measured at V_DD = 2.775V.
Figure 16. “Worst Case” Serializer Test Pattern
t_TLH
V_DIFF 20%
80% 80%
t_THL
20%
V_DIFF = (DS+) – (DS-)
DS+
+
–
5 pF 100Ω
DS-
Figure 17. CTL Output Load and Transition Times
t_ROLH
DPn 20%
80% 80%
t_ROHL
20%
DPn
5pF _1000Ω
Figure 18. LVCMOS Output Load
and Transition Times
©2005 Fairchild Semiconductor Corporation
FIN24C Rev. 1.0.2
18
www.fairchildsemi.com