FIN24C_06 Datasheet, PDF (20/25 Pages) Fairchild Semiconductor – uSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer

AC Loading and Waveforms (Continued)
CKSI-
CKSI+
DSI+
DSI-
t_{S_DS}
V_DIFF=0
V_DIFF=0 V_ID/2
t_{H_DS}
Figure 25. Differential Input Setup and Hold Times
CKSO-
CKSO+
V_DIFF = 0
DSO+
DSO-
V_DIFF = 0
V_ID / 2
t_SK(P-P)
Note: Data is typically edge aligned with the clock.
Figure 26. Differential Output Signal Skew
CKREF
t_TPPLD0
CKS0
Note: CKREF Signal can be stopped either HIGH or LOW.
Figure 27. PLL Loss of Clock Disable Time
t_TPPLD1
S1 or S2
CKS0
Figure 28. PLL Power-Down Time
t_PLZ(HZ)
S1 or S2
t_PZL(ZH)
DS+,CKS0+
DS-,CKS0-
HIGH-Z
Note: CKREF must be active and PLL must be stable.
Figure 29. Serializer Enable and Disable Time
t_PLZ(HZ)
S1 or S2
t_PZL(ZH)
DP
Note: If S1(2) transitioning, S2(1) must = 0 for test to be valid.
Figure 30. Deserializer Enable and Disable Times
©2005 Fairchild Semiconductor Corporation
FIN24C Rev. 1.0.2
20
www.fairchildsemi.com