FIN24C_06 Datasheet, PDF (16/25 Pages) Fairchild Semiconductor – uSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer

AC Electrical Characteristics
Values are provided for over-supply voltage and operating temperature ranges, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min. Typ.⁽⁴⁾ Max. Units
SERIALIZER INPUT OPERATING CONDITIONS
t_TCP CKREF Clock Period
(10 MHz–20 MHz)
See Figure 20
50.0
T
100
ns
f_REF CKREF Frequency Relative to CKREF does not equal STROBE
Strobe Frequency
1.1 x f_ST
20.0 MHz
t_CPWH
t_CPWL
t_CLKT
CKREF Clock High Time
CKREF Clock Low Time
LVCMOS Input Transition
Time
See Figure 20
0.2
0.5
T
0.2
0.5
T
90.0
ns
t_SPWH STROBE Pulse Width
HIGH/LOW
See Figure 20
(T x 4) / 26
(T x 22) / ns
26
f_MAX
t_STC
t_HTC
f_REF
Maximum Serial Data Rate CKREF x 26
DP_(n) Setup to STROBE
DP_(n) Hold to STROBE
CKREF Frequency Relative to
Strobe Frequency
DIRI = 1, See Figure 9 (f = 5MHz)
CKREF Does Not Equal STROBE
SERIALIZER AC ELECTRICAL CHARACTERISTICS
260
2.5
2.0
1.1 x
f_STROBE
520 Mb/s
ns
ns
20.0 MHz
t_TCCD Transmitter Clock Input to
Clock Output Delay
See Figure 23, DIRI = 1,
CKREF = STROBE
t_SPOS CKSO Position Relative to DS See Figure 27⁽⁵⁾
PLL AC ELECTRICAL CHARACTERISTICS
33a + 1.5
–50.0
35a + 6.5 ns
250
ps
t_TPLLS0 Serializer PLL Stabilization
Time
See Figure 22
200
µs
t_TPLLD0 PLL Disable Time Loss of
Clock
See Figure 27
t_TPLLD1 PLL Power-Down Time
See Figure 28⁽⁶⁾
DESERIALIZER INPUT OPERATION CONDITIONS
t_{S_DS} Serial Port Setup Time,
DS-to-CKSI
See Figure 25⁽⁷⁾
t_{H_DS} Serial Port Hold Time,
DS-to-CKS
See Figure 25⁽⁷⁾
1.4
–250
30.0
µs
20.0
ns
ns
ps
DESERIALIZER AC ELECTRICAL CHARACTERISTICS
t_RCOP Deserializer Clock Output
(CKP OUT) Period
See Figure 21
50.0
T
500
ns
t_RCOL CKP OUT Low Time
t_RCOH CKP OUT High Time
See Figure 21 (Rising Edge Strobe)
Serializer Source STROBE = CKREF
Where a = (1 / f) / 26⁽⁸⁾
13a-3
13a-3
13a+3 ns
13a+3 ns
t_PDV Data Valid to CKP LOW
See Figure 21 (Rising Edge Strobe)
Where a = (1 / f) / 26⁽⁸⁾
8a-6
8a+1
ns
t_ROLH Output Rise Time
(20% to 80%)
C_L = 5pF
2.5
ns
t_ROHL Output Fall Time
(80% to 20%)
See Figure 18
2.5
ns
©2005 Fairchild Semiconductor Corporation
FIN24C Rev. 1.0.2
16
www.fairchildsemi.com