FIN24C_06 Datasheet, PDF (19/25 Pages) Fairchild Semiconductor – uSerDes™Low-Voltage 24-Bit Bi-Directional Serializer/Deserializer

AC Loading and Waveforms (Continued)
Setup Time
STROBE
DP[1:12]
t_STC
Data
Hold Time
t_HTC
STROBE
DP[1:12]
Data
Setup: MODE0 = “0” or “1”, MODE1 = “1”, SER/DES = “1”
Figure 19. Serial Setup and Hold Time
Data Valid
CKP
DP[1:12]
t_PDV
Data
t_RCOP
75%
CKP 50%
t_RCOH
50%
25%
t_RCOL
Setup: EN_DES = “1”, CKSI, and DSI are valid signals.
Figure 21. Deserializer Data Valid Window Time
and Clock Output Parameters
t_CLKT
90% 90%
t_CLKT
10%
10%
CKREF _50%
t_TCP
V_IH
t_TCH
V_IL
t_TCL
50%
Figure 20. LVCMOS Clock Parameters
V_DD/V_DDA
S1 or S2
CKREF
t_TPLS0
CKS0
Note: CKREF signal is free running.
Figure 22. Serializer PLL Lock Time
STROBE
CKS0-
CKS0+
V_DD/2
t_TCCD
V_DIFF = 0
Note: STROBE = CKREF
Figure 23. Serializer Clock Propagation Delay
CKSI-
CKSI+
CKP
V_DIFF = 0
t_RCCD
V_DD/2
Figure 24. Deserializer Clock Propagation Delay
©2005 Fairchild Semiconductor Corporation
FIN24C Rev. 1.0.2
19
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