XR20M1172G28-0B Datasheet, PDF (9/55 Pages) Exar Corporation – TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO

XR20M1172
REV. 1.2.0
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
2.1.1.1
I²C-bus Addressing
There could be many devices on the I²C-bus. To distinguish itself from the other devices on the I²C-bus, there
are eight possible slave addresses that can be selected for the M1172 using the A1 and A0 address lines.
Table 1 below shows the different addresses that can be selected. Note that there are two different ways to
select each I2C address.
TABLE 1: XR20M1172 I²C ADDRESS MAP
A1
A0
I²C ADDRESS
VCC
VCC
0x60 (0110 000X)
VCC
GND
0x62 (0110 001X)
VCC
SCL
0x64 (0110 010X)
VCC
SDA
0x66 (0110 011X)
GND
VCC
0x68 (0110 100X)
GND
GND
0x6A (0110 101X)
GND
SCL
0x6C (0110 110X)
GND
SDA
0x6E (0110 111X)
SCL
VCC
0x60 (0110 000X)
SCL
GND
0x62 (0110 001X)
SCL
SCL
0x64 (0110 010X)
SCL
SDA
0x66 (0110 011X)
SDA
VCC
0x68 (0110 100X)
SDA
GND
0x6A (0110 101X)
SDA
SCL
0x6C (0110 110X)
SDA
SDA
0x6E (0110 111X)
An I²C sub-address is sent by the I²C master following the slave address. The sub-address contains the
UART register address being accessed. A read or write transaction is determined by bit-0 of the slave address
(HIGH = Read, LOW = Write). Table 2 below lists the functions of the bits in the I²C sub-address.
TABLE 2: I²C SUB-ADDRESS (REGISTER ADDRESS)
BIT
FUNCTION
7
Reserved
6:3 UART Internal Register Address A3:A0
2:1 UART Channel Select
’00’ = UART Channel A
’01’ = UART Channel B
other values are reserved
0
Reserved
After the last read or write transaction, the I²C-bus master will set the SCL signal back to its idle state (HIGH).
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