XR20M1172G28-0B Datasheet, PDF (46/55 Pages) Exar Corporation – TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO

XR20M1172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
FIGURE 21. SCL DELAY AFTER RESET
RESET#
SCL
TD15
REV. 1.2.0
FIGURE 22. I²C-BUS TIMING DIAGRAM
Protocol
SCL
START
condition
(S)
Bit 7
MSB
(A7)
T_SU;STA
T_LOW T_HIGH
Bit 6
(A6)
1/FSCL
TF
T_R
TBUF
SDA
THD;STA
TSU;DAT
THD;DAT
Bit 0
LSB
(R/W)
Acknowledge
(A)
STOP
condition
(P)
TSP
TVD;DAT
TVD;ACK
TSU;STO
FIGURE 23. WRITE TO OUTPUT
SDA
GPIOn
SLAVE
ADDRESS
W A IOSTATE REG. A
DATA
A
TD1
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