XR20M1172G28-0B Datasheet, PDF (6/55 Pages) Exar Corporation – TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO

XR20M1172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
REV. 1.2.0
1.0 PRODUCT DESCRIPTION
The XR20M1172 (M1172) integrates a selectable I²C/SPI bus interface with an enhanced two-channel
Universal Asynchronous Receiver and Transmitter (UART). The configuration registers set is 16550 UART
compatible for control, status and data transfer. Additionally, each channel of the M1172 has 64-bytes of
transmit and receive FIFOs, automatic RTS/CTS hardware flow control, automatic Xon/Xoff and special
character software flow control, programmable transmit and receive FIFO trigger levels, infrared encoder and
decoder (IrDA 1.0 and 1.1), programmable fractional baud rate generator with a prescaler of divide by 1 or 4,
and data rate up to 16 Mbps with 4X sampling clock rate. The XR20M1172 is a 1.62V to 3.63V device. The
M1172 is fabricated with an advanced CMOS process.
Enhanced Features
The M1172 UART provides a solution that supports 64 bytes of transmit and receive FIFO memory, instead of
16 bytes in the industry standard 16C550. The M1172 is designed to work with low supply voltage and high
performance data communication systems, that require fast data processing time. Increased performance is
realized in the M1172 by the larger transmit and receive FIFOs, FIFO trigger level control and automatic flow
control mechanism. This allows the external processor to handle more networking tasks within a given time.
For example, the 16C550 with a 16 byte FIFO, unloads 16 bytes of receive data in 1.53 ms (This example uses
a character length of 11 bits, including start/stop bits at 115.2 Kbps). This means the external CPU will have to
service the receive FIFO at 1.53 ms intervals. However with the 64 byte FIFO in the M1172, the data buffer will
not require unloading/loading for 6.1 ms. This increases the service interval giving the external CPU additional
time for other applications and reducing the overall UART interrupt servicing time. In addition, the
programmable FIFO level trigger interrupt and automatic hardware/software flow control is uniquely provided
for maximum data throughput performance especially when operating in a multi-channel system. The
combination of the above greatly reduces the CPU’s bandwidth requirement, increases performance, and
reduces power consumption.
The M1172 supports a half-duplex output direction control signaling pin, RTS#, to enable and disable the
external RS-485 transceiver operation. It automatically switches the logic state of the output pin to the receive
state after the last stop-bit of the last character has been shifted out of the transmitter. After receiving, the logic
state of the output pin switches back to the transmit state when a data byte is loaded in the transmitter. The
auto RS-485 direction control pin is not activated after reset. To activate the direction control function, user has
to set EFCR bit-4 to “1”. This pin is HIGH for receive state and LOW for transmit state. The polarity of the
RTS# pin can be inverted via EFCR bit-5.
Data Rate
The M1172 is capable of operation up to 16 Mbps at 3.3V with 4X internal sampling clock rate, 8 Mbps at 3.3V
with 8X sampling clock rate, and 4 Mbps at 3.3V with 16X internal sampling clock rate. The device can operate
with an external 24 MHz crystal on pins XTAL1 and XTAL2, or external clock source of up to 64 MHz on XTAL1
pin. With a typical crystal of 14.7456 MHz and through a software option, the user can set the prescaler bit for
data rates of up to 3.68 Mbps.
The rich feature set of the M1172 is available through the internal registers. Automatic hardware/software flow
control, programmable transmit and receive FIFO trigger levels, programmable TX and RX baud rates, infrared
encoder/decoder interface, modem interface controls, and a sleep mode are all standard features.
Following a power on reset or an external reset, the M1172 is software compatible with previous generation of
UARTs, 16C450, 16C550 and 16C2550.
6