XR20M1172G28-0B Datasheet, PDF (24/55 Pages) Exar Corporation – TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO

XR20M1172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
REV. 1.2.0
2.17 Internal Loopback
The M1172 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 19 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX, RTS# and DTR# pins are held while the CTS#, DSR# CD# and RI# inputs are ignored.
Caution: the RX input pin must be held HIGH during loopback test else upon exiting the loopback test the
UART may detect and report a false “break” signal. Also, Auto RTS/CTS flow control is not supported during
internal loopback.
FIGURE 19. INTERNAL LOOP BACK
Transmit Shift Register
(THR/FIFO)
VCC
MCR bit-4=1
Receive Shift Register
(RHR/FIFO)
VCC
RTS#
CTS#
VCC
DTR#
DSR#
RI#
OP1#
CD#
OP2#
TX
RX
RTS#
CTS#
DTR#
DSR#
RI#
CD#
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