XR20M1172G28-0B Datasheet, PDF (49/55 Pages) Exar Corporation – TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO

REV. 1.2.0
XR20M1172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
AC ELECTRICAL CHARACTERISTICS - SPI-BUS TIMING SPECIFICATIONS
Unless otherwise noted: TA=-40^o to +85^oC, Vcc=1.62 - 3.63V
SYMBOL
PARAMETER
LIMITS
1.8V ± 10%
MIN
MAX
f_SCL SPI clock frequency
8
T_TR CS# HIGH to SO three-state time
100
T_CSS CS# to SCL setup time
100
T_CSH CS# to SCL hold time
20
T_DO SCL fall to SO valid time
30
T_DS SI to SCL setup time
30
T_DH SI to SCL hold time
10
T_CP SCL period time
125
T_CH SCL HIGH time
62
T_CL SCL LOW time
62
T_CSW CS# HIGH pulse width
200
T_D9 SPI output data valid
200
T_D10 SPI modem output data valid
200
T_D11 SPI transmit interrupt clear
200
T_D12 SPI modem input interrupt clear 200
T_D13 SPI input pin interrupt clear
200
T_D14 SPI receive interrupt clear
200
LIMITS
2.5V ± 10%
MIN
MAX
16
100
100
20
20
20
10
63
31
31
200
200
200
200
200
200
200
LIMITS
3.3V ± 10%
MIN
MAX
18
100
100
20
15
15
10
55
27
27
200
200
200
200
200
200
200
UNIT CONDITIONS
MHz
ns C_L = 70 pF
ns
ns
ns C_L = 70 pF
ns
ns
ns
T_CH + T_CL
ns
ns
ns
ns
ns
ns
ns
ns
ns
FIGURE 29. SPI-BUS TIMING
CS#
TCSH
TCSS
SCLK
SI
TDS
TDH
...
TCL
T CH
...
...
SO
...
TCSH
TCSW
TDO
T TR
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