XR20M1172G28-0B Datasheet, PDF (12/55 Pages) Exar Corporation – TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO

XR20M1172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
REV. 1.2.0
2.4 IRQ# Output
The IRQ# interrupt output changes according to the operating mode and enhanced features setup. Table 4
and 5 summarize the operating behavior for the transmitter and receiver. Also see Figures 21 through 35.
TABLE 4: IRQ# PIN OPERATION FOR TRANSMITTER
Auto RS485
Mode
FCR BIT-0 = 0
(NON-FIFO MODE)
FCR BIT-0 = 1
(FIFO MODE)
IRQ# Pin
NO
HIGH = a byte in THR
HIGH = FIFO above trigger level
LOW = THR empty
LOW = FIFO below trigger level or FIFO empty
IRQ# Pin
YES
HIGH = a byte in THR
HIGH = FIFO above trigger level
LOW = transmitter empty LOW = FIFO below trigger level or transmitter empty
TABLE 5: IRQ# PIN OPERATION FOR RECEIVER
IRQ# Pin
FCR BIT-0 = 0
(NON-FIFO MODE)
HIGH = no data
LOW = 1 byte
FCR BIT-0 = 1
(FIFO MODE)
HIGH = FIFO below trigger level
LOW = FIFO above trigger level
The Non-FIFO mode is enabled by default for 16450 compatibility. For normal operation, the FIFO mode must
be enabled.
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