XR20M1172G28-0B Datasheet, PDF (13/55 Pages) Exar Corporation – TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO

XR20M1172
REV. 1.2.0
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
2.5 Crystal Oscillator or External Clock Input
The M1172 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin being the output. Please note that the input XTAL1 is not
5V tolerant and so the maximum at the pin should be VCC. For programming details, see ““Section 2.6,
Programmable Baud Rate Generator with Fractional Divisor” on page 13.”
FIGURE 11. TYPICAL OSCILLATOR CONNECTIONS
XTAL1
XTAL2
R1
0-120 Ω
R2
(Optional)
500 ΚΩ − 1 ΜΩ
C1
22-47 pF
Y1
1.8432 MHz
to
24 MHz
C2
22-47 pF
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100 ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 11). The programmable
Baud Rate Generator is capable of operating with a crystal oscillator frequency of up to 24 MHz. However, with
an external clock input on XTAL1 pin, it can extend its operation up to 64 MHz (16 Mbps serial data rate) at
3.3V with an 4X sampling rate. For further reading on the oscillator circuit please see the Application Note
DAN108 on the EXAR web site at http://www.exar.com.
2.6 Programmable Baud Rate Generator with Fractional Divisor
Each UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter and receiver. The
prescaler is controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide
the input crystal or external clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG further
divides this clock by a programmable divisor between 1 and (2¹⁶ - 0.0625) in increments of 0.0625 (1/16) to
obtain a 16X, 8X or 4X sampling clock of the serial data rate. The sampling clock is used by the transmitter for
data bit shifting and receiver for data sampling. The BRG divisor (DLL, DLM and DLD registers) defaults to the
value of ’1’ (DLL = 0x01, DLM = 0x00 and DLD = 0x00) upon reset. Therefore, the BRG must be programmed
during initialization to the operating data rate. The DLL and DLM registers provide the integer part of the divisor
and the DLD register provides the fractional part of the dvisior. The four lower bits of the DLD are used to select
a value from 0 (for setting 0000) to 0.9375 or 15/16 (for setting 1111). Programming the Baud Rate Generator
Registers DLL, DLM and DLD provides the capability for selecting the operating data rate. Table 6 shows the
standard data rates available with a 24MHz crystal or external clock at 16X clock rate. If the pre-scaler is used
(MCR bit-7 = 1), the output data rate will be 4 times less than that shown in Table 6. At 8X sampling rate, these
data rates would double and at 4X sampling rate, these data rates would quadruple. Also, when using 8X
sampling mode, the bit time will have a jitter of ± 1/16 whenever the DLD is non-zero and is an odd number.
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