XR88C681CP Datasheet, PDF (89/99 Pages) Exar Corporation – CMOS DUAL CHANNEL UART (DUART)

XR88C681
Bit 7
BRG Set
Select
 J 
 J 
Bit 6
Bit 5
Bit 4
Counter/Timer #1 Mode and Source
 Table 7
Bit 3
Delta IP3
Interrupt
J
 J 7
Bit 2
Delta IP2
Interrupt
J
 J 7
Table 35. Auxiliary Control Register: ACR
Bit 1
Delta IP1
Interrupt
J
 J 7
Bit 7
Delta IP3
 J 7
 J G%
Bit 6
Delta IP2
 J 7
 J G%
Bit 5
Delta IP1
 J 7
 J G%
Bit 4
Delta IP0
 J 7
 J G%
Bit 3
IP3
 J 9
 J 8(-
Bit 2
IP2
 J 9
 J 8(-
Table 36. Input Port Configuration Register , IPCR
Bit 1
IP1
 J 9
 J 8(-
Bit 7
Input Port
Change
 J 7
 J G%
Bit 6
Delta Break
B
 J 7
 J G%
Bit 5
RXRDY/
FFULLB
 J 7
 J G%
Bit 4
TXRDYB
 J 7
 J G%
Bit 3
Counter #1
Ready
 J 7
 J G%
Bit 2
Delta Break
A
 J 7
 J G%
Table 37. Interrupt Status Register, ISR
Bit 1
RXRDY/
FFULLA
 J 7
 J G%
Bit 7
Input Port
Change
 J ++
 J 
Bit 6
Delta Break
B
 J ++
 J 
Bit 5
RXRDY/
FFULLB
 J ++
 J 
Bit 4
TXRDYB
 J ++
 J 
Bit 3
Counter #1
Ready
 J ++
 J 
Bit 2
Delta Break
A
 J ++
 J 
Table 38. Interrupt Mask Register, IMR
Bit 1
RXRDY/
FFULLA
 J ++
 J 
Bit 7

.6
Bit 6

.<
Bit 5

.1
Bit 4

.
Bit 3

.
Bit 2

.
Table 39. Counter/Timer Upper Byte Register, CTUR
Bit 1

.
Bit 7

.>
Bit 6

./
Bit 5

.6
Bit 4

.<
Bit 3

.1
Bit 2

.
Table 40. Counter/Timer Lower Byte Register, CTLR
Bit 1

.
Bit 7
#;>
Bit 6
#;/
Bit 5
#;6
Bit 4
#;<
Bit 3
#;1
Bit 2
#;
Table 41. Interrupt Vector Register: IVR
Bit 1
#;
 
=
Bit 0
Delta IP0
Interrupt
J
 J 7
Bit 0
IP0
 J 9
 J 8(-
Bit 0
TXRDYA
 J 7
 J G%
Bit 0
TXRDYA
 J ++
 J 
Bit 0

.=
Bit 0

.
Bit 0
#;