XR88C681CP Datasheet, PDF (77/99 Pages) Exar Corporation – CMOS DUAL CHANNEL UART (DUART)

XR88C681
 (% ( (% % +  -( ' '" ( (  '$ (+  
, ( (% & $'$ (   ! ' '
#+   C2D $ %  %  C*'3D $"    (%
("  ' % ( ( %%$  (   C22
2  D ' $ %  ( 3$ %
% Table 3 Please note that if the Error Mode is “Block”
this bit, in the Status Register will remain set, for all
subsequent characters, independent of the condition of
these received characters, until the “RESET ERROR
STATUS” command has been invoked.
SRn[5] Parity Error
 (% ( (% %     CB#8 , #GD  C 
2
, #GD $%  -$  $ (+  
'% $( - ' ' (   $ #  % '($
( ( '' (&
#+   2 $ %  %  C
'D $"  (%
(  & (%   
'     +   8 #+
 (% ( (% % +  -( ' '" ( (  '$ (+  
'($ (& (% '' (   ! ' '
#+   C2D $ %  %  C*'3D $"    (%
("  ' % ( ( %%$  (   C22
2  D ' $ %  ( 3$ %
% Table 3 Please note that if the Error Mode is “Block”
this bit, in the Status Register will remain set, for all
subsequent characters, independent of the condition of
these received characters, until the “RESET ERROR
STATUS” command has been invoked.
SRn[4] Overrun Error
#+ %"  (% ( ( $('%       ' '% (  
'($ $   %" ( (% %  '( + 
 ' '     #  (% +  $  ' ' (%
$& (    (( - +  & #  %(( 
B   (% ''%"   ' ' (    (% ( 
Please note that unlike the Status Register bits for FE
(Framing Error), PE (Parity Error) and RB (Received
Break), the OE (Overrun Error) indicator is always flagged
on a “Block” Error Mode basis   2 ' $(( (% 
+--$   ' '' ' %(%"  $  &
'$     C22 2  D ' $ (%
( 3$
SRn[3] Transmitter Empty (TXEMT)
 (% ( (% %      %(  $ % # (% %
+  %(%%( +   % % ( +  ' '  $ (+
  (%  ' ' (   8   (( -
 %(%%(   (% ( (% '$      %( (%
$(%$"     
, (%   ' '   
8
SRn[2] Transmitter Ready (TXRDY)
 (% ("   %" ( $('%     8 (% &  $
$&  ''  ' ' +  
,   ( (%
'$    
, (%   ' '    8"
 $ (% %     ' ' (%  %+$    
5G (% %      %( (% ( ((&  $  $
(% %      %( (% $(%$
'%
$$ (    8  (    %( (% $(%$ (
   %($
SRn[1] FIFO Full (FFULL)
 (% ( (% %    ' ' (%  %+$ +  
    8  $    %+ '%% (  ' +"
("    #  %(( %  ''($ # (% %  
 
, $%   8 #+  ' ' (% (( - (  
 '%   #  (% +" 99 (   %
   
, $%   8
SRn[0] Receiver Ready (RXRDY)
 (% ( ( $('%    %   ' ' % 
'($  $ (% (( - (   #    $ &  
,
# (% %    ' ' (%  %+$ +    
  8  $ (% '$ (  
, $%   %
' ' ' & %$ (   # 
Please note that some of the conditions that are flagged
by the Status Register can also be programmed to
generate an Interrupt Request to the CPU. 8"
   % ' $(( %    +--$ &   %
-(%   '   -$  -  
#   % ' $(( %  (%$ 4
  N/O  ( - 2
  N6O  ,(& 2
  N<O   2
 +" (+ %&%  ' '3( - (%  &$"
  % (% ' $$  ($ ' ' ' &
' '3( -   % -(%
 
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