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XR88C681CP Datasheet, PDF (19/99 Pages) Exar Corporation – CMOS DUAL CHANNEL UART (DUART)
XR88C681
 B(  -(' CD  #N>O
ISR[6] Delta Break Indicator - Channel B
B  (% ( (% % " ( ( $(' %       *
 ' (  % $  ' $   -( ( -  $ +   ' ( $
 3 *  (% ( (% '  $   %    ,
( 3 %  '   * C22 *2 : 8 702
#72 ,D ' $ % Table 3  
( +( (    H%  % %   *2 :
' $(( "  % % Section G.2
ISR[5] RXRDY/FFULL B - Channel B Receiver Ready
or FIFO Full
 + '( +  (% ( (% %  ' $ & -( -
*N/O #+ - $ %   ' (   $&
( $(' 5G*" ( ( $(' %     % 
' '  + $ (% ( 8*  $ (%  $&    $ & 
,   (% ( (% %    ' '  (%  %+  $ +
  ' (  % (+  -(%   8*  $ (% '  $ 
 ,  $%  8* #+    %( 
' ' % ( 8* +    $  ( "  ( ( 
%  -( +  8* (% C $D
#+  (% ( (% - $ % #  + ( $('  99*"
( (% %    ' '  (%  %+  $ +   
8*  $   %+  '% % 8*   ' +  (%
( (% '  $   ,  $% 8*L  $   &
C( -D  # " 3( -  +  ! ' '  #+
 ' '  (% (( - (    '% 8* (% +"
 (% ( (  %  -( +    $  ( "   
' '  (% $ $ (  8*
Note:
If this bit is configured to reflect the FFULLB indicator, this
bit will not be set (nor will produce an interrupt request) if
one or two characters are still remaining in RHRB, following
data reception. Hence, it is possible that the last two char-
acters in a string of data (being received) could be lost due
to this phenomenon.
ISR[4] TXRDYB - Channel B Transmitter Ready
 (% ( (%  $(' + 5G *" *NO
 (% ("  % " ( $(' %   8* (% &  $ (%
 $&  ''   ' '  +  ,   ( (%
'  $   , ( %   ' '   8*L
 $ (% %  -( "    ' '  (%  %+  $  
 5G* (% %     %(  (% ( ((&
 $  $ (% '  $    %(  (% $(% $
 ' % $ $ (  8*  (   %(  (%
$(% $ (    %( $
ISR[3] Counter Ready
#  #2 $ "  .   .(  ( % 
#N1O  ' ' '&' +   %  %E 
(   ,1 (  #N1O (  '  $ &
( 3( -  C,  72D ' $ *  ( ( $"
  (  #2 $ "  C,  72D
' $ (  %  .
#   72 $ "  (% ( (% %    '  
 ' %   (  '  /  $ (% '  $ 
 '   (% % $ &  C,  72D
' $ B    .(  (% (   72
$ "  C,  72D ' $ ( % 
  .( 
ISR[2]: Delta Break A - Channel A Change in Break
%% ( +  (% ( ( $(' %    '    ' ( 
% $  ' $   -( ( - +   $ +   ' ( $
 3 *  (% ( (% '  $   , ( 3 % 
'   C22 *2 : 8 702 #72 ,D
' $   ( +( (    H%
 % %   *2 : ' $(( "  % % Section G.2
ISR[1] RXRDYA/FFULL A - Channel A Receiver
Ready or FIFO Full
 + '( +  (% ( (% %  ' $ & -( -
 N/O #+ - $ %   ' (   $&
( $(' 5G "  (% ( ( $(' %     (%   %
 ' '  + $ ( 8 "  $ (%  $&    $ &
 ,   (% ( (% %    ' '  (%  %+  $
+    8  $ (% '  $   ,
 $%  C%D 8  #+    %(  ' ' %
( 8 " +( -   $  ( "  ( (  % 
-( +  8 (% C $D
#+  (% ( (% - $ %  #  8 + ( $('
 99 " ( (% %    ' '  (%  %+  $ +
   8  $  &  %+  $ ' ' 
'% % 8   ' +  (% ( (% '  $  
,  $% 8  #+  ' '  (% (( - (  
 '% 8 (% +"  (% ( (  %  -( " +( -
  $  ( "    ' '  (% $ $ ( 
8 
Note:
If this bit is configured to reflect the FFULLA indicator, this
bit will not be set (nor will produce an interrupt request) if