XRT94L33_2 Datasheet, PDF (701/810 Pages) Exar Corporation – 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER - SDH REGISTERS

Rev222...000...000
XRT94L33
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Table 501: Receive STM-0 Section – Receive SF Clear Monitor Interval – Byte 2 (Address Location=
0xN15D, where N ranges in value from 0x05 to 0x07)
BIT 7
R/W
1
BIT 6
R/W
1
BIT 5
BIT 4
BIT 3
BIT 2
SF_CLEAR_MONITOR_WINDOW[23:16]
R/W
R/W
R/W
R/W
1
1
1
1
BIT 1
R/W
1
BIT 0
R/W
1
BIT NUMBER
7-0
NAME
SF_CLEAR_MONITOR_WINDOW
[23:16]
TYPE
DESCRIPTION
R/W SF_CLEAR_MONITOR_INTERVAL – MSB:
These READ/WRITE bits, along the contents of the
“Receive STM-0 Section – SF Clear Monitor Interval – Byte
1 and Byte 0” registers permit the user to specify the length
of the “monitoring period” (in terms of ms) for SF (Signal
Failure) defect clearance.
When the Receive STM-0 SOH Processor block is
checking the incoming STM-0 signal in order to determine if
it should clear the SF defect condition, it will accumulate B2
byte errors throughout the user-specified “SF Defect
Clearance” Monitoring period. If, during this “SF Defect
Clearance” Monitoring period, the Receive STM-0 SOH
Processor block accumulates less B2 byte errors than that
programmed into the “Receive STM-0 Section SF Clear
Threshold” register, then the Receive STM-0 SOH
Processor block will clear the SF defect condition.
NOTES:
1. The value that the user writes into these three (3)
“SF Clear Monitor Window” Registers, specifies
the duration of the “SF Defect Clearance
Monitoring Period”, in terms of ms.
2. This particular register byte contains the “MSB”
(Most significant byte) value of the three registers
that specify the “SF Defect Clearance Monitoring”
period.
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