XRT94L33_2 Datasheet, PDF (591/810 Pages) Exar Corporation – 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER - SDH REGISTERS

Rev222...000...000
XRT94L33
333---CCCHHHAAANNNNNNEEELLL DDDSSS333///EEE333///SSSTTTSSS---111 TTTOOO SSSTTTSSS---333///SSSTTTMMM---111 MMMAAAPPPPPPEEERRR ––– SSSDDDHHH RRREEEGGGIIISSSTTTEEERRRSSS
Table 418: Receive DS3/E3 Interrupt Status Register – Secondary Frame Synchronizer Block (Address
Location= 0xN3F9, where N ranges from 0x02 to 0x04)
BIT 7
Unused
R/O
0
BIT 6
Change of
LOS Defect
Condition
Interrupt
Status
RUR
0
BIT 5
Change of
AIS Defect
Condition
Interrupt
Status
RUR
0
BIT 4
Change of
DS3 Idle
Condition
Interrupt
Status
RUR
0
BIT 3
BIT 2
Unused
R/O
R/O
0
0
BIT 1
Change of
OOF Defect
Condition
Interrupt
Status
RUR
0
BIT 0
Unused
R/O
0
BIT NUMBER
7
NAME
Unused
6
Change of LOS Defect
Condition Interrupt Status
5
Change of AIS Defect
Condition Interrupt Status
TYPE
R/O
DESCRIPTION
RUR
Change of LOS Defect Condition Interrupt Status – Secondary
Frame Synchronizer Block:
This RESET-upon-READ bit-field indicates whether or not the
“Change of LOS Defect Condition” Interrupt (per the Secondary
Frame Synchronizer block) has occurred since the last read of this
register.
0 – Indicates that the “Change of LOS Defect Condition” Interrupt
(per the Secondary Frame Synchronizer block) has NOT occurred
since the last read of this register.
1 – Indicates that the “Change of LOS Defect Condition” Interrupt
(per the Secondary Frame Synchronizer block) has occurred since
the last read of this register.
Note:
The user can determine the current state of “LOS Defect”
(per the Secondary Frame Synchronizer” block) by
reading out the state of Bit 6 (Secondary Frame
Synchronizer – LOS Defect Declared) within the Receive
DS3/E3 Status Register – Secondary Frame
Synchronizer block” register (Address Location=
0xN3F1).
RUR
Change of AIS Defect Condition Interrupt Status – Secondary
Frame Synchronizer Block:
This RESET-upon-READ bit-field indicates whether or not the
“Change of AIS Defect Condition” Interrupt (per the Secondary
Frame Synchronizer block) has occurred since the last read of this
register.
0 – Indicates that the “Change of AIS Defect Condition” Interrupt
(per the Secondary Frame Synchronizer block) has NOT occurred
since the last read of this register.
1 – Indicates that the “Change of AIS Defect Condition” Interrupt
(per the Secondary Frame Synchronizer block) has occurred since
the last read of this register.
Note:
The user can determine the current state of “AIS Defect”
(per the Secondary Frame Synchronizer” block) by
reading out the state of Bit 7 (Secondary Frame
Synchronizer – AIS Defect Declared) within the Receive
DS3/E3 Status Register – Secondary Frame
Synchronizer block” register (Address Location=
0xN3F1).
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