XRT94L33_2 Datasheet, PDF (65/810 Pages) Exar Corporation – 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER - SDH REGISTERS

Rev222...000...000
Bit 2
Bit 1
Bit 0
XRT94L33
333---CCCHHHAAANNNNNNEEELLL DDDSSS333///EEE333///SSSTTTSSS---111 TTTOOO SSSTTTSSS---333///SSSTTTMMM---111 MMMAAAPPPPPPEEERRR ––– SSSDDDHHH RRREEEGGGIIISSSTTTEEERRRSSS
STM-0
Telecom Bus
Parity Odd
STM-0
Telecom Bus
Parity Disable
STM-0
REPHASE
OFF
R/W
R/W
R/W
“STS1RXD_C1J1_2” output coincident to whenever the C1 and J1
bytes are being output via the “STS1RXD_2_D[7:0]” output pins.
b. The Transmit STM-0 Telecom Bus Interface will expect the
“STS1TXA_C1J1_2” input to be pulsed “high” coincident to
whenever the C1 and J1 bytes are being sampled via the
“STS1TXA_2_D[7:0]” input pins.
1 – J1 Bytes Only
This selection configures the following.
a. The Receive STM-0 Telecom Bus Interface to only pulse the
“STS1RXD_C1J1_2” output pin coincident to whenever the J1 byte
is being output via the “STSRXD_2_D[7:0]” output pins.
Note: In this setting, the “STS1RXD_C1J1_2” output pin will NOT be
pulsed “high” whenever the C1 byte is being output via the
“STS1RXD_D_2[7:0]” output pins
b. The Transmit STM-0 Telecom Bus Interface will expect the
“STS1TXA_C1J1_2” input to only be pulsed “high” coincident to
whenever the J1 byte is being sampled via the
“STS1TXA_2_D[7:0]” input pins.
Note: In this setting, the “STS1TXA_C1J1_2” input pin will NOT be
pulsed “high” whenever the C1 byte is being input via the
“STS1TXA_2_D[7:0]” input pins
STM-0 Telecom Bus Interface Parity – ODD Parity Select – Channel 2:
This READ/WRITE bit-field permits the user to configure the STM-0
Telecom Bus Interface, associated with Channel 2 to do the following.
In the Receive (Drop) Direction
Receive STM-0 Telecom Bus Interface will compute either the EVEN or
ODD parity over the contents of the (1) STS1RxD_2_D[7:0] output pins, or
(2) STS1RxD_2_D[7:0] output pins, the states of the STS1RxD_PL_2 and
STS1RxD_C1J1_2 output pins (depending upon user setting for Bit 3).
In the Transmit (Add) Direction
Transmit STM-0 Telecom Bus Interface will compute and verify the EVEN or
ODD parity over the contents of the (1) STS1TxA_2_D[7:0] input pins, or (2)
STS1TxA_2_D[7:0] input pins, the states of the STS1TxA_PL_2 and
STS1TxA_C1J1_2 input pins (depending upon user setting for Bit 3).
0 – Configures Receive STM-0 (Drop) Telecom Bus Interface to compute
EVEN parity and configures the Transmit STM-0 (Add) Telecom Bus
Interface to verify EVEN parity.
1 – Configures Receive STM-0 (Drop) Telecom Bus Interface to compute
ODD parity and configures the Transmit STM-0 (Add) Telecom Bus
Interface to verify ODD parity.
STM-0 Telecom Bus Interface - Parity Disable – Channel 2:
This READ/WRITE bit-field permits the user to either enable or disable
parity calculation and placement via the “STSRxD_DP_2” output pin.
Further, this bit-field also permits the user to enable or disable parity
verification via the “STS1TxA_DP_2” input pin by the Transmit Telecom
Bus.
1 – Disables Parity Calculation (on the Receive Telecom Bus) and Disables
Parity Verification (on the Transmit Telecom Bus.
0 – Enables Parity Calculation and Verification
STM-0 Telecom Bus Interface – Rephase Disable – Channel 2:
This READ/WRITE bit-field permits the user to configure the Receive STM-0
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