XRT94L33_2 Datasheet, PDF (394/810 Pages) Exar Corporation – 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER - SDH REGISTERS

XRT94L33
333---CCCHHHAAANNNNNNEEELLL DDDSSS333///EEE333///SSSTTTSSS---111 TTTOOO SSSTTTSSS---333///SSSTTTMMM---111 MMMAAAPPPPPPEEERRR ––– SSSDDDHHH RRREEEGGGIIISSSTTTEEERRRSSS
Rev222...000...000
interrupt has occurred since the last read of this register.
Note:
The user can determine if the Receive TUG-3/AU-3 Mapper VC-3
POH Processor block is currently declaring the AU-LOP/TU-LOP
defect condition by reading out the state of Bit 1 (AU-LOP/TU-
LOP Defect Declared) within the “Receive TUG-3/AU-3 Mapper
VC-3 Path – SONET Receive POH Status – Byte 0” Register
(Address Location= 0xN187).
0
Change of AU- RUR Change of AU-AIS/TU-AIS Defect Condition Interrupt Status:
AIS/TU-AIS
Defect Condition
Interrupt Status
This RESET-upon-READ bit-field indicates whether or not the “Change of
AU-AIS/TU-AIS Defect Condition” Interrupt has occurred since the last read
of this register.
If this interrupt is enabled, then the Receive TUG-3/AU-3 Mapper VC-3
POH Processor block will generate an interrupt in response to either of the
following events.
• Whenever the Receive TUG-3/AU-3 Mapper VC-3 POH Processor block
declares the AU-AIS/TU-AIS defect condition.
• Whenever the Receive TUG-3/AU-3 Mapper VC-3 POH Processor block
clears the AU-AIS/TU-AIS defect condition.
0 – Indicates that the “Change of AU-AIS/TU-AIS Defect Condition”
Interrupt has NOT occurred since the last read of this register.
1 – Indicates that the “Change of AU-AIS/TU-AIS Defect Condition”
Interrupt has occurred since the last read of this register.
Note:
The user can determine if the Receive TUG-3/AU-3 Mapper VC-3
POH Processor block is currently declaring the AU-AIS/TU-AIS
defect condition by reading out the state of Bit 0 (AU-AIS/TU-AIS
Defect Declared) within the “Receive TUG-3/AU-3 Mapper VC-3
Path – SONET Receive POH Status – Byte 0” Register (Address
Location= 0xN187).
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