XRT94L33_2 Datasheet, PDF (480/810 Pages) Exar Corporation – 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER - SDH REGISTERS

XRT94L33
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1.10.5 RECEIVE E3, ITU-T G.832 RELATED REGISTERS
Rev222...000...000
Table 316: RxE3 Configuration and Status Register # 1 – G.832 (Address Location= 0xN310, where N
ranges from 0x02 to 0x04)
BIT 7
BIT 6
BIT 5
RxPLDType[2:0]
R/O
R/O
R/O
0
1
0
BIT 4
RxFERF
Algo.
R/W
0
BIT 3
RxTMark
Algo
R/W
0
BIT 2
BIT 1
RxPLDTypeExp[2:0]
BIT 0
R/W
R/W
R/W
0
1
0
BIT NUMBER
7-5
4
3
2-0
NAME
RxPLDType[2:0]
RxFERF Algo
RxTMark Algo
RxPLDTypExp[2:0]
TYPE
R/O
R/W
R/W
R/W
DESCRIPTION
Received PLD (Payload) Type[2:0]:
These three READ-ONLY bit-fields reflect the value of the Payload Type
bits, within the MA byte of the most recently received E3 frame.
Receive FERF/RDI Defect Declaration/Clearance Algorithm:
This READ/WRITE bit-field permits the user to select a “FERF/RDI Defect
Declaration and Clearance” Algorithm, as indicated below.
0 – Configures the Primary Frame Synchronizer block to declare the
FERF/RDI defect condition anytime that it receives the FERF/RDI
indicator in 3 consecutive E3 frames. Additionally, this same setting will
also configure the Primary Frame Synchronizer block to clear the
FERF/RDI defect condition if it no longer receives the FERF/RDI indicator
(within the E3 data-stream) for 3 consecutive E3 frames.
1 – Configures the Primary Frame Synchronizer block to declare the
FERF/RDI defect condition anytime it receives the FERF/RDI indicator
(within the incoming E3 data-stream) in 5 consecutive E3 frames.
Additionally, this same seting will also configure the Primary Frame
Synchronizer block to clear the FERF/RDI defect condition anytime it
ceases to receive the FERF/RDI indicator for 5 consecutive E3 frames.
Receive Timing Marker Validation Algorithm:
This READ/WRITE bit-field permits the user to select the “Receive Timing
Marker Validation” algorithm, as indicated below.
0 – The Timing Marker will be validated if it is of the same state for three
(3) consecutive E3 frames.
1 – The Timing Marker will be validated if it is of the same state for five (5)
consecutive E3 frames.
Receive PLD (Payload) Type – Expected:
This READ/WRITE bit-field permits the user to specify the “expected
value” for the Payload Type, within the MA bytes of each incoming E3
frame. If the Primary Frame Synchronizer block receives a Payload Type
that differs then what has been written into these register bits, then it will
generate the “Payload Type Mismatch” Interrupt.
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