XRT94L33_2 Datasheet, PDF (274/810 Pages) Exar Corporation – 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER - SDH REGISTERS

XRT94L33
333---CCCHHHAAANNNNNNEEELLL DDDSSS333///EEE333///SSSTTTSSS---111 TTTOOO SSSTTTSSS---333///SSSTTTMMM---111 MMMAAAPPPPPPEEERRR ––– SSSDDDHHH RRREEEGGGIIISSSTTTEEERRRSSS
Rev222...000...000
Table 168: Redundant Receive STM-1 Section – B1 Byte Error Count Register – Byte 2 (Address
Location= 0x1711)
BIT 7
RUR
0
BIT 6
RUR
0
BIT 5
RUR
0
BIT 4
BIT 3
B1_Byte_Error_Count[23:16]
RUR
RUR
0
0
BIT 2
RUR
0
BIT 1
RUR
0
BIT 0
RUR
0
BIT NUMBER
7-0
NAME
B1_Byte
Error_Count
[23:16]
TYPE
RUR
DESCRIPTION
B1 Byte Error Count (Bits 23 through 16):
This RESET-upon-READ register, along with “Redundant Receive STM-1
Section – B1 Byte Error Count Register – Bytes 3, 1 and 0; function as a 32 bit
counter, which is incremented anytime the Redundant Receive STM-1 SOH
Processor block detects a B1 byte error.
Note:
1. If the Redundant Receive STM-1 SOH Processor block is configured to
count B1 byte errors on a “per-bit” basis, then it will increment this 32-bit
counter by the number of bits, within the B1 byte (of each incoming STM-1
frame) that are in error.
2. If the Redundant Receive STM-1 SOH Processro block is configured to
count B1 byte errors on “per-frame” basis, then it will increment this 32-bit
counter each time that it receives an STM-1 frame that contains an erred B1
byte.
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