XRT94L33_2 Datasheet, PDF (310/810 Pages) Exar Corporation – 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER - SDH REGISTERS

XRT94L33
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Table 206: Redundant Receive STM-1 Section – Receive SD Clear Monitor Interval – Byte 0 (Address
Location= 0x175B)
BIT 7
R/W
1
BIT 6
R/W
1
BIT 5
R/W
1
BIT 4
BIT 3
BIT 2
SD_CLEAR_MONITOR_WINDOW[7:0]
R/W
R/W
R/W
1
1
1
BIT 1
R/W
1
BIT 0
R/W
1
BIT NUMBER
7-0
NAME
SD_CLEAR_MONITOR_WINDOW[
7:0]
TYPE
R/W
DESCRIPTION
SD_CLEAR_MONITOR_INTERVAL – LSB:
These READ/WRITE bits, along the contents of the
“Redundant Receive STM-1 Section – SD Clear Monitor
Interval – Byte 2 and Byte 1” registers permit the user to
specify the length of the “monitoring period” (in terms of
ms) for SD (Signal Degrade) defect clearance.
When the Redundant Receive STM-1 SOH Processor
block is checking the incoming STM-1 signal in order to
determine if it should clear the SD defect condition, it will
accumulate B2 byte errors throughout the user-specified
“SD Defect Clearance” Monitoring period. If, during this
“SD Defect Clearance Monitoring” period, the Redundant
Receive STM-1 SOH Processor block accumulates less
B2 byte errors than that programmed into the “Redundant
Receive STM-1 Section SD Clear Threshold” register,
then the Redundant Receive STM-1 SOH Processor block
will clear the SD defect condition.
NOTES:
1. The value that the user writes into these three (3)
“SD Clear Monitor Window” Registers, specifies
the duration of the “SD Defect Clearance
Monitoring Period”, in terms of ms.
2. This particular register byte contains the “LSB”
(least significant byte) value of the three registers
that specify the “SD Defect Clearance
Monitoring” period.
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