XR17V254 Datasheet, PDF (69/70 Pages) Exar Corporation – 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT

PRELIMINARY
XR17V254
REV. 1.0.0
66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT
BIT FORMAT................................................................................................................................................... 28
TABLE 11: TRANSMIT AND RECEIVE DATA REGISTER IN BYTE FORMAT, 16C550 COMPATIBLE .......................................................... 28
4.0 UART...................................................................................................................................................... 29
4.1 PROGRAMMABLE BAUD RATE GENERATOR WITH FRACTIONAL DIVISOR ........................................... 29
FIGURE 11. BAUD RATE GENERATOR ............................................................................................................................................. 30
TABLE 12: TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING ................................................. 30
4.2 AUTOMATIC HARDWARE (RTS/CTS OR DTR/DSR) FLOW CONTROL OPERATION................................. 31
FIGURE 12. AUTO RTS/DTR AND CTS/DSR FLOW CONTROL OPERATION...................................................................................... 32
4.3 INFRARED MODE ............................................................................................................................................. 33
FIGURE 13. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING.......................................................................... 33
4.4 INTERNAL LOOPBACK.................................................................................................................................... 34
FIGURE 14. INTERNAL LOOP BACK ................................................................................................................................................. 34
4.5 UART CHANNEL CONFIGURATION REGISTERS AND ADDRESS DECODING .......................................... 34
TABLE 13: UART CHANNEL CONFIGURATION REGISTERS. .................................................................................................. 35
TABLE 14: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED BY EFR BIT-4. ....... 36
4.6 TRANSMITTER.................................................................................................................................................. 37
4.6.1 TRANSMIT HOLDING REGISTER (THR)..................................................................................................................... 37
4.6.2 TRANSMITTER OPERATION IN NON-FIFO MODE .................................................................................................... 37
FIGURE 15. TRANSMITTER OPERATION IN NON-FIFO MODE ............................................................................................................ 38
4.6.3 TRANSMITTER OPERATION IN FIFO MODE ............................................................................................................. 38
4.6.4 AUTO RS485 OPERATION .......................................................................................................................................... 38
FIGURE 16. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE ................................................................................... 38
4.7 RECEIVER ......................................................................................................................................................... 39
4.7.1 RECEIVER OPERATION IN NON-FIFO MODE .......................................................................................................... 39
FIGURE 17. RECEIVER OPERATION IN NON-FIFO MODE.................................................................................................................. 39
4.7.2 RECEIVER OPERATION WITH FIFO........................................................................................................................... 40
FIGURE 18. RECEIVER OPERATION IN FIFO AND FLOW CONTROL MODE ......................................................................................... 40
5.0 UART CONFIGURATION REGISTERS ................................................................................................ 40
5.1 RECEIVE HOLDING REGISTER (RHR) - READ ONLY ................................................................................... 40
5.2 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY ............................................................................... 40
5.3 BAUD RATE GENERATOR DIVISORS (DLM, DLL AND DLD)....................................................................... 40
5.4 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ................................................................................ 40
5.4.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 40
5.4.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION.................................................................. 41
5.5 INTERRUPT STATUS REGISTER (ISR) - READ ONLY .................................................................................. 42
5.5.1 INTERRUPT GENERATION: ........................................................................................................................................ 42
5.5.2 INTERRUPT CLEARING: ............................................................................................................................................. 42
TABLE 15: INTERRUPT SOURCE AND PRIORITY LEVEL ..................................................................................................................... 43
5.6 FIFO CONTROL REGISTER (FCR) - WRITE ONLY......................................................................................... 43
TABLE 16: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION .......................................................................... 45
5.7 LINE CONTROL REGISTER (LCR) - READ/WRITE ........................................................................................ 45
TABLE 17: PARITY PROGRAMMING ................................................................................................................................................. 46
5.8 MODEM CONTROL REGISTER (MCR) - READ/WRITE .................................................................................. 47
5.9 LINE STATUS REGISTER (LSR) - READ ONLY.............................................................................................. 48
5.10 MODEM STATUS REGISTER (MSR) - READ ONLY ..................................................................................... 49
5.11 MODEM STATUS REGISTER (MSR) - WRITE ONLY.................................................................................... 50
TABLE 18: AUTO RS485 HALF-DUPLEX DIRECTION CONTROL DELAY FROM TRANSMIT-TO-RECEIVE ................................................. 51
5.12 SCRATCH PAD REGISTER (SPR) - READ/WRITE ....................................................................................... 52
5.13 FEATURE CONTROL REGISTER (FCTR) - READ/WRITE ........................................................................... 52
TABLE 19: 16 SELECTABLE HYSTERESIS LEVELS WHEN TRIGGER TABLE-D IS SELECTED ................................................................ 53
5.14 ENHANCED FEATURE REGISTER (EFR) - READ/WRITE ........................................................................... 53
TABLE 20: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 55
5.15 TXCNT[7:0]: TRANSMIT FIFO LEVEL COUNTER - READ ONLY ................................................................ 55
5.16 TXTRG [7:0]: TRANSMIT FIFO TRIGGER LEVEL - WRITE ONLY ............................................................... 55
5.17 RXCNT[7:0]: RECEIVE FIFO LEVEL COUNTER - READ ONLY................................................................... 55
5.18 RXTRG[7:0]: RECEIVE FIFO TRIGGER LEVEL - WRITE ONLY .................................................................. 55
5.19 XOFF1, XOFF2, XON1 AND XON2 REGISTERS, WRITE ONLY................................................................... 55
5.20 XCHAR REGISTER, READ ONLY .................................................................................................................. 56
TABLE 21: UART RESET CONDITIONS ...................................................................................................................................... 57
ABSOLUTE MAXIMUM RATINGS ................................................................................. 58
ELECTRICAL CHARACTERISTICS............................................................................... 58
DC ELECTRICAL CHARACTERISTICS FOR 3.3V SIGNALLING................................................................. 58
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