XR17V254 Datasheet, PDF (65/70 Pages) Exar Corporation – 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT

REV. 1.0.0
XR17V254
66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT
FIGURE 24. TRANSMIT DATA INTERRUPT AT TRIGGER LEVEL
START
BIT
DATA BITS (5-8)
STOP
BIT
TX Data
D0 D1 D2 D3 D4 D5 D6 D7
5 DATA BITS
PARITY
BIT
6 DATA BITS
7 DATA BITS
NEXT
DATA
START
BIT
TX Interrupt at
Transmit Trigger Level
Set at Below
Trigger Level
Clear at
Above
Trigger Level
BAUD RATE CLOCK of 16X or 8X
TXNOFIFO-1
FIGURE 25. RECEIVE DATA READY INTERRUPT AT TRIGGER LEVEL
START
BIT
DATA BITS (5-8)
STOP
BIT
RX Data Input
D0 D1 D2 D3 D4 D5 D6 D7
PARITY First byte that
BIT reaches the
trigger level
RX Data Ready Interrupt at
Receive Trigger Level
De-asserted at
below trigger level
Asserted at
above trigger
level
RXFIFO1
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