XR17V254 Datasheet, PDF (55/70 Pages) Exar Corporation – 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT

XR17V254
REV. 1.0.0
66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT
EFR[3:0]: Software Flow Control Select
Combinations of software flow control can be selected by programming these bits, as shown in Table 20
below.
TABLE 20: SOFTWARE FLOW CONTROL FUNCTIONS
EFR BIT [3]
0
0
1
0
1
X
X
X
1
0
1
0
EFR BIT [2]
0
0
0
1
1
X
X
X
0
1
1
0
EFR BIT [1] EFR BIT [0] TRANSMIT AND RECEIVE SOFTWARE FLOW CONTROL
0
0
No TX and RX flow control (default and reset)
X
X
No transmit flow control
X
X
Transmit Xon1, Xoff1
X
X
Transmit Xon2, Xoff2
X
X
Transmit Xon1 and Xon2, Xoff1 and Xoff2
0
0
No receive flow control
1
0
Receiver compares Xon1, Xoff1
0
1
Receiver compares Xon2, Xoff2
1
1
Transmit Xon1, Xoff1
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1
1
Transmit Xon2, Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1
1
Transmit Xon1 and Xon2, Xoff1 and Xoff2
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
1
1
No transmit flow control
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
5.15 TXCNT[7:0]: Transmit FIFO Level Counter - Read Only
Transmit FIFO level byte count from 0x00 (LOW) to 0x40 (64). This 8-bit register gives an indication of the
number of characters in the transmit FIFO. The FIFO level Byte count register is read only. The user can take
advantage of the FIFO level byte counter for faster data loading to the transmit FIFO, which reduces CPU
bandwidth requirements.
5.16 TXTRG [7:0]: Transmit FIFO Trigger Level - Write Only
An 8-bit value written to this register sets the TX FIFO trigger level from 0x00 (zero) to 0x40 (64). The TX FIFO
trigger level generates an interrupt whenever the data level in the transmit FIFO falls below this preset trigger
level.
5.17 RXCNT[7:0]: Receive FIFO Level Counter - Read Only
Receive FIFO level byte count from 0x00 (zero) to 0x40 (64). It gives an indication of the number of characters
in the receive FIFO. The FIFO level byte count register is read only. The user can take advantage of the FIFO
level byte counter for faster data unloading from the receiver FIFO, which reduces CPU bandwidth
requirements.
5.18 RXTRG[7:0]: Receive FIFO Trigger Level - Write Only
An 8-bit value written to this register, sets the RX FIFO trigger level from 0x00 (zero) to 0x40 (64). The RX
FIFO trigger level generates an interrupt whenever the receive FIFO level rises to this preset trigger level.
5.19 XOFF1, XOFF2, XON1 AND XON2 REGISTERS, WRITE ONLY
These registers are used to program the Xoff1, Xoff2, Xon1 and Xon2 control characters respectively.
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