XR17V254 Datasheet, PDF (48/70 Pages) Exar Corporation – 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT

XR17V254
66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT
REV. 1.0.0
MCR[3]: Send Char Immediate (OP2 in Local Loopback Mode)
This bit is used to transmit a character immediately irrespective of the bytes currently in the transmit FIFO. The
data byte must be loaded into the transmit holding register (THR) immediately following the write to this bit (to
set it to a ’1’). In other words, no other register must be accessed between setting this bit and writing to the
THR. The loaded byte will be transmitted ahead of all the bytes in the TX FIFO, immediately after the character
currently being shifted out of the transmit shift register is sent out. The existing line parameters (parity, stop
bits) will be used when composing the character. This bit is self clearing, therefore, must be set before sending
a custom character each time. Please note that the Transmitter must be enabled for this function (MSR[3] = 0).
Also, if software flow control is enabled, the software flow control characters (Xon, Xoff) have higher priority
and will get shifted out before the custom byte is transmitted.
• Logic 0 = Send Char Immediate disabled (default).
• Logic 1 = Send Char Immediate enabled.
In Local Loopback Mode (MCR[4] = 1), this bit acts as the legacy OP2 output and controls the CD bit in the
MSR register as shown in Figure 14. Please make sure that this bit is a ’0’ when exiting the Local Loopback
Mode.
MCR[2]: DTR# or RTS# for Auto Flow Control (OP1 in Local Loopback Mode)
DTR# or RTS# auto hardware flow control select. This bit is in effect only when auto RTS/DTR is enabled by
EFR bit [6]. DTR# selection is associated with DSR# and RTS# is with CTS#.
• Logic 0 = Uses RTS# and CTS# pins for auto hardware flow control.
• Logic 1 = Uses DTR# and DSR# pins for auto hardware flow control.
In Local Loopback mode (MCR[4] = 1), this bit acts as the legacy OP1 output and controls the RI bit in the MSR
register, as shown in Figure 14.
MCR[1]: RTS# Output
The RTS# pin may be used for automatic hardware flow control by enabled by EFR bit [6] and MCR bit [2]=0. If
the modem interface is not used, this output may be used for general purpose.
• Logic 0 = Force RTS# output to a HIGH (default).
• Logic 1= Force RTS# output to LOW.
MCR[0]: DTR# Output
The DTR# pin may be used for automatic hardware flow control enabled by EFR bit [6] and MCR bit [2]=1. If
the modem interface is not used, this output may be used for general purpose.
• Logic 0 = Force DTR# output to a HIGH (default).
• Logic 1 = Force DTR# output to a LOW.
5.9 Line Status Register (LSR) - Read Only
This register provides the status of data transfers between the UART and the host. If IER bit [2] is set to a
logic 1, an LSR interrupt will be generated immediately when any character in the RX FIFO has an error (parity,
framing, overrun, break).
LSR[7]: Receive FIFO Data Error Flag
• Logic 0 = No FIFO error (default).
• Logic 1 = An indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error or
break indication is in the FIFO data. This bit clears when there are no more errors in the FIFO.
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