XR17V254 Datasheet, PDF (29/70 Pages) Exar Corporation – 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT

XR17V254
REV. 1.0.0
66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT
4.0 UART
There are 4 UARTs channel [3:0] in the V254. Each has its own 64-byte of transmit and receive FIFO, a set of
16550 compatible control and status registers, and a baud rate generator for individual channel data rate
setting. Eight additional registers per UART were added for the EXAR enhanced features.
4.1 Programmable Baud Rate Generator with Fractional Divisor
Each UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter and receiver. The
prescaler is controlled by a software bit in the MCR register. The MCR register bit [7] sets the prescaler to
divide the input crystal or external clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG
further divides this clock by a programmable divisor between 1 and (2¹⁶ - 0.0625) in increments of 0.0625 (1/
16) to obtain a 16X or 8X sampling clock of the serial data rate. The sampling clock is used by the transmitter
for data bit shifting and receiver for data sampling. The BRG divisor (DLL, DLM and DLD registers) defaults to
a random value upon power up. Therefore, the BRG must be programmed during initialization to the operating
data rate. The DLL and DLM registers provide the integer part of the divisor and the DLD register provides the
fractional part of the divisor. Only the four lower bits of the DLD are implemented and they are used to select a
value from 0 (for setting 0000) to 0.9375 or 15/16 (for setting 1111). Programming the Baud Rate Generator
Registers DLL, DLM and DLD provides the capability for selecting the operating data rate. Table 12 shows the
standard data rates available with a 14.7456 MHz crystal or external clock at 16X clock rate. If the pre-scaler is
used (MCR bit [7] = 1), the output data rate will be 4 times less than that shown in Table 12. At 8X sampling
rate, these data rates would double. Also, when using 8X sampling mode, please note that the bit-time will
have a jitter (+/- 1/16) whenever the DLD is an odd number. When using a non-standard data rate crystal or
external clock, the divisor value can be calculated with the following equation(s):
Required Divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16), WITH 8XMODE [7:0] IS 0
Required Divisor (decimal) = (XTAL1 clock frequency / prescaler / (serial data rate x 8), WITH 8XMODE [7:0] IS 1
The closest divisor that is obtainable in the V254 can be calculated using the following formula:
ROUND( (Required Divisor - TRUNC (Required Divisor) )*16)/16 + TRUNC (Required Divisor), where
DLM = TRUNC( Required Divisor) >> 8
DLL = TRUNC (Required Divisor) & 0xFF
DLD = ROUND ( (Required Divisor-TRUNC(Required Divisor) )*16)
In the formulas above, please note that:
TRUNC (N) = Integer Part of N. For example, TRUNC (5.6) = 5.
ROUND (N) = N rounded towards the closest integer. For example, ROUND (7.3) = 7 and ROUND (9.9) = 10.
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