XR17V254 Datasheet, PDF (20/70 Pages) Exar Corporation – 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT

XR17V254
66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT
REV. 1.0.0
Timer Operation in Re-triggerable Mode:
In the re-triggerable mode, when the Timer is started, the Timer output will stay HIGH until it reaches half of the
terminal count N (= P clocks) and toggle LOW and stay LOW for a similar amount of time (Q clocks). The
above step will keep repeating until the Timer is stopped at which time the output will become HIGH (default
state). See Figure 7. Also, after the Timer is started, re-starting the Timer does not have any effect in re-
triggerable mode. The Timer must be programmed while it is stopped since the following operations are
blocked when the Timer is running:
■ Any write to TIMER MSB, LSB registers
■ Issue of any command other than ’Stop Timer’ and ’Reset Timer’ (’Start Timer’ is not allowed)
Routing the Timer Output to MPIO[0] Pin:
MPIO[0] pin is by default (on power up or reset, for example) an input. However, whenever the Timer output is
routed to MPIO[0] pin,
■ MPIO[0] will be automatically selected as an output
■ MPIO[0] will become HIGH (the default state of Timer output)
■ All MPIO control registers (MPIOLVL, MPIOSEL etc) lose control over MPIO[0] and get the control back
only when the Timer output is de-routed from MPIO[0].
FIGURE 7. TIMER OUTPUT IN ONE-SHOT AND RE-TRIGGERABLE MODES
TIMER Output in
One-Shot Mode
START TIMER
COMMAND ISSUED
START TIMER COMMANDS ISSUED: LESS THAN 'N'
CLOCKS BETWEEN SUCCESSIVE COMMANDS
START TIMER
COMMAND ISSUED
'N' Clocks
< 'N' Clocks
< 'N' Clocks
STOP TIMER
COMMAND ISSUED
TIMER Output in
Re-triggerable
Mode
After 'P'
clocks
After 'P'
clocks
After 'P'
clocks
After 'P'
clocks
After 'P'
clocks
After 'Q'
clocks
After 'Q'
clocks
After 'Q'
clocks
After 'Q'
clocks
Timer Interrupt
In the one-shot mode, the Timer will issue an interrupt upon timing out which is ’N’ clocks after the Timer is
started. In the re-triggerable mode, the Timer will keep issuing an interrupt every ’N’ clocks which is on every
rising edge of the Timer output. The Timer interrupt can be cleared by reading the TIMERCNTL register or
when a Timer Reset command is issued which brings the Timer back to its default settings. The TIMERCNTL
will read a value of 0x01 when the Timer interrupt is enabled and there is a pending interrupt. It reads a value
of 0x00 at all other times. Stopping the Timer does not clear the interrupt and neither does subsequent re-
starting.
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