XR21B1422IL40-0A Datasheet, PDF (58/60 Pages) Exar Corporation – Enhanced 2-Ch Full-Speed USB UART

Bit
1:0
Default
0
Not used
Description
XR21B1422
PIN_CFG_RS485_POL (0x033) - Read/Write OTP
This register configures the polarity of the selected auto RS-485 half-duplex control pin.
Bit
7:1
0
Default
Description
0
Reserved
These bits are reserved and should be written as ’0’.
0
POL
0: Active low auto. RS-485 half-duplex enable
1: Active high auto. RS-485 half-duplex enable
CLK_DIV (0x034) - Read/Write OTP
This register sets the default clock divisor for the CLK output.
Bit
7:0
Default
Description
0
VALUE
Output clock frequency will be determined by the formula:
FREQ = 24 MHz / 2 * (VALUE). If VALUE = 0, FREQ = 24 MHz
Application Circuits
The GPIO inputs are 5V tolerant. However, when GPIO input voltage levels exceed VIO, an external clamp circuit is
required to prevent VIO from increasing. Two examples of different application circuits are shown in Figure 7.
VIO Clamp Circuits
1=;9$
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9,2
1
© 2014 Exar Corporation
Figure 7: VIO Clamp Circuits
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Rev 1A